"NU180" - A U180 drop-in replacement for the 3458A.

[IanJ]

You guys may have already answered the following in your NU180 designs, but I thought I'd mention what's come to mind for me:

- Make sure there are no unintentional islands (copper pour).
- Are return paths adequate?
- Is there any inadequate supply decoupling? Too high ESR of caps used can cause timing edge ringing.
- Any requirement for trace length matching?
- Any unhelpful trace crossovers?
- JTAG header/signal too close to the 734's possibly?

Anyways, great work so far, I'm following along intently!

Ian.

[DB4UCH]

Some updates from my NU180:

I repeated the INL measurement, and, other than the gain error for different signs, it’s looking great! (I basically hit the noise / TC limit of my system). The INL tracks down to less than +-0.2PPM of FS to my 34401A. I attached the three graphs below.

I also did a noise measurement like Kleinstein recommended. (1NPLC, shorted input, AZ on)

I also attached the graph from this measurement below.

I also attached the TC for CAL 72 over a few days. No long-term drift was noticeable during this time.

I will now attempt to measure DNL and then see if I can change the gain behavior by adding a resistor in series with the clock signal. @Kleinstein I would have used a 100-200 Ohms resistor. Do you think that value is in the right order of magnitude?

Greetings,
Simon

[Kleinstein]

The 1 PLC noise looks like some 9-10 µV_pp (exculding rare extremes). This would correspond to some 1.4 µV RMS. This a quite a bit higher than what is normally found with the 3458 ( 500-600 nV RMS for 20 ms integration AZ).  So the noise seems to be not as good as the orignal.  There could still be some background interference signal (e.g. temperature fluctuations), not just pure noise.

Some resistors can also show significant excess noise, as a kind of 1/f noise from the resistors  (80 K and 10K/10K inverter part). This would cause even more noise for the 10 PLC case.

100-200 ohms are already on the high side and can cause additional jitter. So far I have seem more like 22 or 33 ohms in the clock lines.

[Zondar]

DB4UCH: You say "shorted input" but also "10V range." Are both true? If so, your noise is 1.38 uV RMS or 0.138 ppm RMS of the 10V range. This is above but reasonably close to the specification of the 3458A, which is slightly below 0.1 ppm of range, i.e. 1 uV (from the "additional errors" chart).

It's still early days in this adventure, so things will still improve, but a very important point to remember is that being close to spec is infinitely better than a non-working A3 board!

Yes, as you slow down edges, jitter will increase. Although we haven't measured that or compared anything that may influence it yet, it's best practice to use the smallest control-signal resistor values that will permit reliable operation. But I wonder why inserting a resistor in series with the clock line could help. I didn't put any there - did you build that in from the start? What is the rationale?

[DB4UCH]

DB4UCH: You say "shorted input" but also "10V range." Are both true? If so, your noise is 1.38 uV RMS or 0.138 ppm RMS of the 10V range. This is above but reasonably close to the specification of the 3468A, which is slightly below 0.1 ppm of range, i.e. 1 uV (from the "additional errors" chart).

Yes, both are true, the 3458A is set to the 10V range and the inputs are shorted with a piece of copper wire. (like the recommended short for the zero calibration that's described in the cal manual)

Yes, as you slow down edges, jitter will increase. Although we haven't measured that or compared anything that may influence it yet, it's best practice to use the smallest control-signal resistor values that will permit reliable operation. But I wonder why inserting a resistor in series with the clock line could help linearity, etc. I didn't put any there - did you build that in from the start? What is the rationale?

I will just cut the trace (on MiDis board it's on the bottom layer) and hack in a resistor directly. But before that I will try to load the clock signal with a 10:1 scope probe. As for why this could affect linearity, if the clock could maybe get mixed down with a phase shifted version of itself / some other harmonic and create some sort of low frequency / dc component somewhere. This mixing can happen anywhere where you have some sort of nonlinear component. (So basically in every semiconductor) Although I don't know if that is the reason tbh.

Greetings,
Simon

[Zondar]

OK, got it. None of these boards will be as clean as U180 is due to its higher integration, so it's worth looking at things like this. I doubt you will see any difference, but it will be very interesting if you do.

Also, wanghar: Wow, you went to the ADG734's! Nice looking board, too. It's very curious that it seemed to help. I found the 788's to be a huge pain when routing, partly due to the thermal pad being in the way, to the point that the space-savings wasn't as great as hoped. (Actually, I wonder why a thermal pad is needed with these sub uW switches - did you use and ground them?) The 734's are much easier to design with, and far easier to hand-solder if necessary.

One suggestion: The decoupling caps need to be right on the supply pins, especially for the CPLD. You seem to have some either absent or somewhat further from the pins than optimum.

What are you referring to by "the current compensation circuit on the A3 board," the input FET modulation? Something else?

[Kleinstein]

The noise specs are for < 750 nV RMS for 1 PLC 10 V and shorted. So the 1.38 µV is roughly 2 x the specs.
Actual measurements on newer using with 50 Hz and thus 20 ms for 1 PLC often gave noise more on the 500-600 nV range. With 60 Hz and thus a bit shorter integration the noise is naturally a bit higher (some 10%)
1.4 µV noise level is similar to or a bit worse than the KS3446x.

It is still better to have the 3458 working with additional noise than just failing.
Higher noise us still limiting the value: 2 x the noise needs 4 x the integration time for the same noise in the result.

The idea with the resistor is increasing reverse isolation. Reflection from the CPLD back to the oscillator is one way to get clock modulation. The other path is residual signal via the supply or ground and it is a bit hard predict which way is more relevant.  So the extra resistor could make a difference or not. It is still a point that can be tested relatively easy. Even if only a partial reduction of the INL it would give a hint on where to look.

The is ground current compensaton (for the ZR_low = GNG sense from A9 module) with R168 (10.2 K) on the A3 baord. This is to compensate the current through the 6 K+4.14 K for the 7 to 12 V gain step. So when using different values (e.g. 6.8 K and 4.7 K) one may want to adjust R168.

[iMo]

..
One suggestion: The decoupling caps need to be right on the supply pins, especially for the CPLD. You seem to have some either absent or somewhat further from the pins than optimum..

What are the values of the decoupling caps at your boards? When with a higher value - like 1u - I would use 2 caps in parallel, like 10n+1u with the 10n closer to the pin.

[Zondar]

The noise specs are for < 750 nV RMS for 1 PLC 10 V and shorted. So the 1.38 µV is roughly 2 x the specs.

Where do you see that? I haven't found anything better than the "additional errors" chart, which is a pretty poor reference.

I think even 2x is fantastic at this early stage of development.

iMo: I used 0.1 uF in 603 size for general decoupling. This is not optimal, actually, but it's a simple and common choice that is hand-solderable. I would reconsider a lot of things if/when I made a substantially different board.

[Zondar]

Simon: I looked at the clock right at the CPLD with a 1 pF active probe, ~1 GHz bandwidth. It looks really good, with virtually no ringing or reflections, etc., visible. Try it if you like, of course, but I doubt you will find a benefit by adding a resistor.

I also looked at how much my 100 Ohm resistors slowed down control signals: It changed from about 3.5 ns rise-time prior to the resistor to about 4.7 after. I used a 220 Ohm resistor on that one particularly sensitive control line (I didn't have much else) and that slowed it down to 10 ns. I will soon try a few different values for that.

[DB4UCH]

I measured the DNL using a triangular signal (from 0V to 10mV @ 1Hz) at 0.01 NPLC in the 10V range. This voltage range should cover the rundown, which is responsible for the LSBs. (I think about half of the bits (the LSBs) are acquired during the rundown, the other half during the runup with the big slopes). But I also quickly checked with a ramp from 0V to 100mV, and didn’t see missing codes either, but that’s over the limit that makes sense with my 12 Bit DDS generator.

The result is the following: LSB of ~14µV, seemingly no missing codes and a pretty flat distribution in the histogram. This LSB corresponds to a resolution of ~20.7 bits, so quite close to the specified 21 bits from the datasheet.

From this I would conclude that the small slopes / rundown seem to be working like intended.

I attached a few histograms below; those histograms were created using a bit over 500k samples. (The base with the minimum number of bins (707), and "zoomed" in variants where I increased the number of bins to get more details. The histogram with the larger binning that isn't zoomed in shows some aliasing, but that’s due to the limited plot resolution.

Greetings,
Simon

[wanghar]

Also, wanghar: Wow, you went to the ADG734's! Nice looking board, too. It's very curious that it seemed to help. I found the 788's to be a huge pain when routing, partly due to the thermal pad being in the way, to the point that the space-savings wasn't as great as hoped. (Actually, I wonder why a thermal pad is needed with these sub uW switches - did you use and ground them?) The 734's are much easier to design with, and far easier to hand-solder if necessary. 

Generally speaking, for the same die, if it comes in both LFCSP (or DFN) and TSSOP packages, the performance metrics of the LFCSP/DFN version tend to be slightly better. I still think that if there were no startup error, the performance of the ADG788 would have been somewhat better than that of the ADG734.

One suggestion: The decoupling caps need to be right on the supply pins, especially for the CPLD. You seem to have some either absent or somewhat further from the pins than optimum.

All four decoupling caps for the PLD are present, though they're placed a bit further away from the chip. This was mainly for easier manual soldering and chip replacement. There's definitely room for optimization. Also, 4pcs of decoupling caps for the ADG734s are mounted on the bottom side of the board due to limited space on the top.

[wanghar]

Noise test at 10V range, 1PLC, with input shorted. The noise rms measures around 940nV, which is a bit higher than the original 3458A, but still acceptable. When performing the test, make sure to install the aluminum shield plate above the A3 board.

[Kleinstein]

940 nV rms noise for the 1 PLC is not that bad. For many uses (highest resolution) the 10 PLC case would be more relevant and this part has additional 1/f noise (from the integrator LT1001, the main amplifier and to a lesser degree the LT1001 to do the 12 to -12 V step).
Unless there is additional 1/f noise from poor resistors, the 10 PLC case is expected to be closer to the noise specs.

[DB4UCH]

One small thing I noticed with my board: Attaching scope probes to the control input of the switches for the 80ks sometimes changed the direction of the gain error and also sometimes made it worse. (Depending on the specific switch, with S11 there wasn't any noticeable change)
Playing around with the clock didn't change anything.
So, I guess we might have some slight timing issues? Or EMI? I will now play around with the values of the control resistors (so therefore changing the risetimes) and see if that allows me to decrease the gain error.

The trace lengths on my board are: S11: 28.1mm S9: 11.7mm S7: 11.3mm S5: 23mm.

I attached graphs for the changed INL values below. (The specific switch that was probed is in the filename.)

Greetings,
Simon

[Sorama]

I knew it from the start;you guys are all crazy as hell!
But deepest respect anyway.
 

[Kleinstein]

It is interesting that just probing the control signals has that much effect and that the effect is such a simple abs(U) form.

Capacitive coupling from the control signals to the switches is part of the charge-injection to the Integrator. Loading the signals can add extra capacitive coupling and slow down the switching, which may effect the charge injection part inside the switch. With the extra level shifter stage inside the ADG734/788 I would not expect that much effect from the switch internal part.

I don't see timing issues directly at the control signals. Just a little different delay between the signals should not change anything in the simple picture of the integrator. It would change the charge injection, especially at the very short time scale (<10 ns range). If the charge pulse gets too large this may drive the integrator input to beyound some +-20 mV and the input of the OP-amps in the integrator may get nonlinear.  The number of switching events is constant and just changing the charge injection would to a 1st approximation only add an offset, but should hardly change much that is voltage dependent.

A point that changes with the voltage and may follow about the abs(U) form is the number of double short pulse for the reference switching. So a short positive ref. pulse followed by a short negative pulse and/or the other way around. This should still be pulses of some 200 ns and thus long compared to the rise/fall times at the controll signals. The double pulses could have a tiny effect with settling at the integrator, but this should not depend on the timing detail. Another effect could be with supply ripple as swiching give extra supply current. Especially with the rather low R switches I don't see enough to cause so much INL error. Capacitive loading could change the current needed.

[Zondar]

Simon: That's excellent work! Keep it up! I think you are on the verge of cracking an important problem or two! 

Maybe better digital signal conditioning is all it will take. Otherwise, we might have to assert more definitive control over the switches.

I knew it from the start;you guys are all crazy as hell!
But deepest respect anyway.
 

Speaking for myself, I'm past certifiable! 

[MiDi]

My x180 resistor network version is a fail.

   

Comparison of the S64 slope U180 vs x180: x180 has only half the slope rate and runs into timeout after 800ns (throws 114 rundown convergence error).
The ladder resistor values are nearly the same for both (37.5k & 16.7k).
The scope is set w/o BW limit for comparing the ringing - both look similar.





How is that possible?
Some simulations later showed the major culprit are the parasitic capacitances on the junctions of 16.7k and 37.5k ladder resistors.
The measured capacitance between lad (pin 23) and gnd1 is around 180pF for x180, original U180 has around 14pF.
With capacitive compensation across the 37.5k lad resistor, S64 looks much better, but S16 is too steep and has this large jump when switched in.



At least the ladder resistors need a redesign with as low stray capacitance as possible.
The ±12ref resistors switching on the opposite look similar to the other designs, but maybe could benefit from lower stray capacitance to reduce the switching spikes?

[DB4UCH]

I did some more probing and found out that I was able to improve the gain error by probing directly on the input of the 100 Ohms resistors of S11 and S9 (so on the CPLD side).
Therefore, I attempted to slightly slow down both switches by increasing the series resistance.
I attached INL sweeps below for various values: 118 Ohms (4x 470 Ohms in parallel as I don't have any other value on hand in the proper size) seemed to perform the best, for much larger values of the resistor (156 Ohms and 235 Ohms) a reversal and increase of the gain error was noticeable. From this I estimate the optimal resistance value to be in the 120 to 140 Ohms range.  I will order a few different resistors and try to find the optimum for my specific board. (Cleaning the NU180 with IPA to remove the flux residue made the gain error a bit worse again, I attached plots for both)

@MiDi
Just for comparison I attached two screenshots from my scope measuring: S64, S16, the slope amp and the integrator directly (TP 112). One for a failed conversion, the other for a working one. Those measurements were taken before I modified my A3 board with the capacitor at the slope amp.
(Your error 117 seems to be a typo?)
The slope rate at the integrator for my NU180 seems to lie somewhere between your NU180 and your original U180. (Closer to the latter)

Greetings,
Simon

[Kleinstein]

@MIDI
There is a lot of ringing / oscillation background on the signals. Not sure if the background is real, or just an artifact of probing a signal that has a lot of oscillation (e.g. channel4 - maybe the comparator output). Some signals may already be effected by probing - so they could be OK if no probed.

The extra capacitance of the resistor array could be an issue. So keeping the circuit small has a good reason.

@DB3uch

Trimming the series resistors for the drive signals would only be a last resort, as it would be quite some effort and it is not clear if the INL would stay exactly as trimmed or change with the temperature. ideally one would understand the mechanism behind the extra abs(U) part and avoid it all together. After all it looks like the original U180 get away without it and it looks like the  3458 seems to have not separate adjustment for the positive and negative gain. Some other meters may support that.

For the ADC I see 2 properties that change roughly like abs(U):
1) the number of cases where a short positive and negative reference pulse come to close togeter. This happen with a change between a positive and negative run-up step (one direction). This happens the most in the center and no longer at the extremes.
The double short phases may have an INL effect via settling at the integrator and via supply ripple (more switching in a short time).

2) the maximum voltage at the integrator output should also roughly scale like abs(U) and follow a run-up step plus the input signal.
With the non inverting slope amplifier the amount of ground current from the slope amplifier would scale with the amplitude.

[MiDi]

(Your error 117 seems to be a typo?)

Indeed it is 114, corrected it.

@MIDI
There is a lot of ringing / oscillation background on the signals. Not sure if the background is real, or just an artifact of probing a signal that has a lot of oscillation (e.g. channel4 - maybe the comparator output). Some signals may already be effected by probing - so they could be OK if no probed.

The extra capacitance of the resistor array could be an issue. So keeping the circuit small has a good reason.

The ringing is present on several signals, e.g. +5ref and between gnd and zr_lo (reference gnd) with both U180 and x180.
The ref voltages and the integrator are referenced to zr_lo.
There might be some influence from bad probing, the probes and scope, but with 20MHz BW limit it looks much smoother:

[DB4UCH]

A short update: I noticed quite some ringing on the GND plane (on the GND side of C192 for example) during the switching of the S256 slopes. (>400mVpp) (I don't know how a real U180 performs in this regard, but this could be part of the issue)

Another thing: connecting the various GNDs with a small 39pF capacitor showed the following: GND or AGND3 to AGND 1&2 made the gain error worse. (By a factor of about 2) The other combinations didn't change much at all. I also attempted removing the capacitor I put on the slope amp, but other than not running reliable anymore, no change was observable.

An improvement with the gain error could be observed by connecting SUM1 / 2 with AGND 1. The error was halved in this case. I attached an INL plot of the current state.
I don't really know what to take from this other than that the switches might be too fast, leading to more ringing? I am completely out of my depth here.

@Kleinstein
Do you have anything specific in mind you want me to try / measure?

Thanks, and Greetings,
Simon

[Kleinstein]

400 mV of ripply between different ground sounds horrible. There may still be a probing issue. If it is really that bad one should be able to see the waveform and if it is more main hum, the 20 kHz clock the 330 kHz modulation or the more triangle integrator output.

Ripple between the different grounds could be a real issue. I lost a bit track of the actual circuits used. One point with ground ripple could be if there are no isolating resistors in the 5 V supply to the CPLD and switches. This way decoupling capacitors would be at a relatively noisy supply and couple the noise to ground. One may also want separate isolation for the CPLD and the switches.

A point to test could be to add additional decoupling (e.g. at the CPLD, e.g. 1 or 2 µF extra) and compare the INL before after with otherwise identical conditions (e.g. no extra probes). This would give a hint if supply decoupling is a factor.

To check if the ground current from the slope amplifier is a factor, one could add a little extra resistor (e.g. 10 K range) from the slope amplifier to ground (near the 1 K link to ground that is already there). This would about double to ground current from that source.

I also don't have a clear idea what could cause the abs(U) part, especially as it seems to follow the abs(U) law that accurate.
The 2 short pulses part would likely mainly have an effect via supply ripple on the somewhat longer time scale around 0.5 µs. So not  the super fast part but more a point where the capacitance can make a difference.  The ringing at the integrator should be less of an issue as this would need an effect over 2 x 200 ns and this time should be good enough for settling.

I just relatized a potential issue with the CPLD: it looks like there are a few unused pins (e.g. the ones for programming). If they have only rather weak pull-up / pull downs these may be sensitive to capacitive coupling to fast edge signals. Especially a signal driven negative or beyond the supply could influence other pins via substrate current. I don't know why this would give an abs(U) part, but it could at least be an avoidable possible weak point.

From may ADC I faintly remember a still small improvement in the INL a bit like an abs(U) part from additional decoupling at the clock, even with the canned oscillator. However this is at a lower level, but also with only ÀC74 flip flops and not a CPLD loading the clock and I have less frequent switching. I had a cleat effect with the poor bare crystal oscillator. So an effect back to the clock is still a candidate. This could be via the supply, via ground or via the clock signal.
Depending on the revision the oscillator and U180 (VDD1) seem to use a common supply filter (via ferrite L230). So there may be relatively poor supply isolation from U180 to the clock and stronger supply spikes with the NU180 compared to the original U180 are well possible.
 Using a different path to get the 5 V to the NU180 maybe worth a test.

[wanghar]

During INL testing on board #5（V0.3 PCB）, I did observe a noticeable change in the gain when measuring negative voltages as Simon and Zondar posted before. This change in gain appears to be solely related to voltage polarity. It looks like there's a systematic bug that needs to be fixed. However, calculations show that the negative voltage still maintains fairly good linearity between 0V and -10V. Test images are attached.

Within the 0V to +10V range, board #5 also demonstrated excellent linearity. In comparison tests with another 3458A over the full scale, the differences were all less than 1 µV. This translates to an INL of less than 0.1 ppm across the entire 0V to 10V range. The setup for this comparison test was identical to the previous test on board #2:
https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6080173/#msg6080173
And the results are highly consistent with the earlier findings, test image is also attached.

It's important to note that increasing the resistor values between the CPLD and the ADG734/788 reduces the probability of Error 114（S11 control line）, but this increase in resistance also has a potentially negative impact on INL performance. Probably makes sense to keep the values of these resistors consistent.

Additionally, further testing was conducted on the 10V range with the input shorted at 10 PLC. The noise RMS level was measured to be approximately 350-370 nV.