DIY high resolution multi-slope converter

[Kleinstein]

A short up-date:

I noticed that the 74LV4053 chips from Ti and Nexperia are different: the Ti part is relatively low resistance (23 ohms typ) the Nexperial part is considerable higher resistance (old 70 Ohms , new even higher in the datasheet). So the switch chip should be the Ti version, or other manufacturer with low R_on.

Attached is an update to the software - mainly for the PC side. The PC side program is for Freepascal/Lazarus and can also run under Win10 and similar and support USB to UART converters.  The µC part has not changed much, mainly going towards slower modulation (change in the constant xdel and maybe a few updated comments). The µC and PC side have to match in this respect, so both sides are included.

Slower modulation reduces the noise a little (less noise from jitter). The INL is expected to get a little better for the switching effects and a little worse for the capacitor DA (likely the smaller part with a good capacitor).

I am currently working on a version with STM32L0x1 µC and a DVM input section. Except for the µC and some required level translation not much change for the hardware side. But things are slow with poor parts availability  (even MCP6001 were out of stock at mouser  ).

[Kleinstein]

Here a short teaser about the front end: The curve shows the discharge of a 1000 pF capacitor connected to the input.
For the start the capacitor is charged to a voltage near the full range.
The slope of the curve is an indication of the input current for the voltmeter.

The observed leakage is quite a bit better then the specs of the parts used. So I may just have been lucky here.
The curve deviates a bit from a simple exponential RC discharge, as there is some extra bias current and also variations in the leakage resistance with time and voltage.

[DeltaSigmaD]

Some aspects of theory of high-resolution ADCs here should be discussed.

The leakage current of an integration capacitor is usually no problem for ADCs, e.g. >1 TOhm for a  600V WIMA MKP4. With my measurements, the time constant of such capacitors was much higher than the 8h specified in the data sheet. However, the dielectric absorption of the capacitor is a real problem for a switched-current-integrator topology if the integrator output voltage is evaluated. The dielectric absorption causes a non-linearity as function of capacitor voltage and timing. This effect can be suppressed if the mean value at the capacitor is kept constant while the "timing" is also well-controlled. "Timing" must be explained: the voltage across the capacitor must have no frequency components which have a lower frequency than a frequency where the suppression by a suitable digital lowpass filter is already sufficiently high. A Delta-Sigma technology satisfies this demand directly, and the suppression of the digital filter can be easily better than 120dB.

Common to high-res ADCs discussed here is the first analog current integrator. As far as I know, the differences between the 2 main technologies are :

1. Multiple-slope technique: the integrator output voltage is digitised with an ADC, and a digital algorithm is applied to derive a suitable timing of switch control. This algorithm is essential to avoid that the non-linearity by dielectric absorption is folded down to the final conversion result. The nonlinearity can be reduced by dividing the digitisation in a coarse and fine step. Coarse step: the input signal is integrated, and the integrator output is kept at low absolute voltage by applying relatively large, constant, and extremely reproducible charge portions. The duty cycle of the charge balance pulses must not be >0.5, since additional non-linearity is induced by small pulse pauses. Fine step: a down-scaled reference current is used to measure the remaining charge (for instance a charge-to-time conversion). In most designs the input signal must be disconnected from the first integrator, which point is a considerable disadvantage. The discontinuous integration is equivalent to the input modulation with a square wave with accordingly huge mixing products. The integrator voltage change during the fine step is small enough to obtain low non-linearity.

2. Continuous-time Delta-Sigma technique (CTDS): the output voltage of the first integrator is further integrated by one or more additional analog integrators (integrator chain). The timing of switches is derived from a weighted sum of integrator voltages (analog modulator output). Together with the feedback via the switches a stable mixed analog/digital filter with a well-defined filter function is formed. Higher order filters (3 or more) are prone to latch-up (caused by over-voltage), but it is simple to stop any latch-up. The CTDS-ADC performs a continuous integration of the input signal. Fine conversion steps are not required, high resolution is indirectly derived from timing. The errors of the digitisation step (required to get the switch control signals) are filtered by a third or higher order highpass.

An additional third method shall be proposed, which is a certain combination of the 2 methods above:
3. The input signal is continuously integrated by only one analog integrator. The integrator output is digitised by a fast high-resolution ADC. The ADC output is integrated at least by 2 additional digital integrators, and the latter digital signals are combined to a digital modulator output (third or higher order). Closing the control loop via current switches, the errors of the ADC are highpass filtered, but only with 1st order filtering. The differential linearity of the ADC is essential for obtaining low "noise" at medium frequency. The output result is extracted from the switch control by suitable digital lowpass filtering (4th order or higher). 

It seems that the MS-ADC shown in this forum doesn't follow one of these techniques. A FPGA or uC is used to control the switches. I would be interested on the theory behind this control which is essential for good linearity. Are there publications describing this?

[Echo88]

  JFET-Frontend based on a existing known design like 34420A i expect? Or is it something of your own cooking?

[Kleinstein]

The dielectric absorbtion can cause some INL errors, but with a good grade capacitor the INL problem due to DA is not so extreme. I totally agree that reducing the average voltage in the capacitor is a good idea to suppress the DA effect. This does not have to be perfect and already a moderate improvement (e.g. a factor of 2)  would help. I don't think intrinsic capacitor leakage is a big problem, but it is a possible error source and external leakage, e.g. on the board can add to the capacitor itself. The integration cap is relatively small (e.g. 2.2 nF here) with a MS ADC. So it does not take much boad leakage (100 G range) to cause trouble. A reduced average voltage would also help against this leakage part. Leakage is kind of zero frequency DA.

For the classical muli-slope ADC, as is the HP 3458, 3456, Keithley200x or Fluke8845 as examples there is no auxiliary ADC. The integrator is reset to zero and charge after run-up is measured for the time needed to discharge back to zero. For more resolution 1 or more fine slopes are used.

The ADC in the HP 34401 (Multislope 3, continuous integrating) is continuously integrating like an SD ADC and uses an auxiliiary ADC to measure the charge at the start and stop. So there is no reset and also no fine slope. The feedback during run-up is still from a comparator and with a simple modulation with 2 extreme PWM cases: eihter mainly positve or mainly negative, but no in between cases.

There is a similarity to the old mark-space ADC in the Solartron DMMs: these also use continuous integration, but the feedback is with a more continuous PWM modulation and a much slower modulation. The final charge reading is from just the exact timing for zero crossing. Because of the rather limited resolution these ADCs need a rather long integration (e.g. a few seconds to 50 seconds for a single conversion). These DMMs have relatively high noise (low speed), but good INL despite the simple circuit. The rather accurate feedback avoids DA related errors despite the slow modulation.

The ADC proposed/shown in this thread is a bit in between the classical MS ADC and the HP3401: using a seprate rundown with a slow slope, but no reset and a reading of an auxiliary ADC instead. So it is a bit different.
The modulation in the run-up is the same as with many MS ADC: the 2 extremes and a comparator to decide, as this is the easiest to implement. The ADC started off as a simple solution - it only later turned out that is works quite well.

The sigma delta ADC is kind of similar to the MS-3 with contiuous integration, but usually with additional integrators and also looking at more than just the first and last zero crossing / charge reading to get more information to use in a higher order digital filter. The classical form uses just on/off moduation and a rather fast modulation. More advanced forms may use PWM modulation an an ADC for the feedback. The theoretical background is in the frequency domain. The noise shaping idea works well with an AC signal present and on average over many input voltages. However it does not work that good with constant input signal at some special levels. This causes a rather low frequency signal (idele tone) at the integrator output and quite some swing and still possible DA related or similar problems, so the SD ADC is not immune to the problems. In modern SD chips the idle tones are suppressed with more or less secret / patented techniques, like dithering. I think some of the INL errors I see look quite a bit like the idele tones in a simple SD ADC.

In many DMMs there is an Auto zero cycle around the ADC. So the input signal is not continuous sampled, but there is switching between the input signal an zero. So there is some modulation and possible aliasing from the input. So the additional, relatively short run-down phase (e.g. some 100 µs to 1 ms) does not make a realy different with some thing line 20 ms input and 20 ms zero integration. Switching and initial filter settling also need extra time with some SD ADCs. So there usually still is a dead time in between.

I don't think the DA is really the limiting factor to the INL - faster modulation is a kind of brute force way to reduce DA effects. The weak points are more settling of the integrator input and coupling through the supplies and ground.  Also the resistance of the FET switches is a potential source of INL. A better modulation to avoid DA effects can still be interesting, as it could allow a slower modulation and thus less switching related errors. A more contineous PWM and control from an auxiliary ADC (or the comparator timing) would be an option. This does not really need an extra analog integrator, one could get a good approximation for every cycle.

[Kleinstein]

JFET-Frontend based on a existing known design like 34420A i expect? Or is it something of your own cooking?

The front end is probably a bit similar to the input of the Sigilent SDM3068 and Rigol3065. I don't know the details there, but they only have a +-15 V supply and still get a +-20 V (+ some overrange) with high input impedance. So I expect them to use a similar configuration, though with a differential ADC and an additional divider stage and possibly no gain. With a differential ADC the input configuration is a little more obvious - it is one known way to suppress the common mode signal, when you have floating signal source.

To get the large input range the low side is not fixed at ground but driven to -1/2 the input voltage. So the signals to the ADC are +1/2 the input voltage and -1/2 the input voltage. Instead of the classical signal and zero AZ loop the ADC read +- half the input. The resistors to set the 1/2 factor are not critical as the difference does not depend on the resistors. The input amplifier is an AD8628 Az OP (like in the SDM3068) with a bootstrapped supply and a 2nd OP to make it a compound amplifier and drive the full output range. With an ADC that can read up to about +-12 V this gives a +-24 V range with high input impedance. The switching at the input is kept to a minimum ( 1 JFET (on) and 2 CMOS (off) switches are at the input). The 2nd CMOS switch is not even absolutely needed, but there for a 2nd input. The observed bias level is still a positive surprise and likely with quite some luck. I had expected slightly more (e.g. 20-50 pA range). Input protection is with MOSFETs and PV opto-couplers, a bit like some Keithley (200x) meters to keep resistor noise low, though at the cost of not that perfect a protection.

A nice side effect of the configuration is that 2 ADC readings are summed up and the input is sampled for most of the time (e.g. 2x20 ms out of some 41 ms). This reduces the noise bandwidth for the input and this also applies to the input amplifier for ranges with gain. So the relatively low bias AD8628 OP can give a pretty low noise also for the 2V and 200 mV range. It would not directly compete with the 34420 in the 1 and 10 mV ranges, but still pretty low noise.

[DeltaSigmaD]

@Kleinstein:
Thanks for the overview of AD technologies used by DMMs.

One thing I want to comment: it is not too complicated to obtain a continuous-time Delta-Sigma ADC (CTDS) almost free of idle tones. The modulator should have third or better forth order. The first integrator must be sufficiently linear, what can be obtained with a composite amplifier. The open loop gain is typically >300dB. If there is no parasitic feedback, for instance by stray capacitance in the fF range, the latch-up eliminator, or power supply lines, then the idle tones are forced into a higher frequency range where they are suppressed by the digital filter. It might be interesting, at least some of the PREMA DMMs had an only 2nd order modulator, so that idle tones had to be present and the measurement rate for high resolution was very slow compared to competing DMMs. PREMA called the technique not DS - I assume that this was a kind of work-around for american patents active at that time. Due to parasitic coupling, it seems to be very expensive to use CTDS-technique on an integrated circuit (see e.g. "Wide-Bandwidth Single-Bit Continuous-Time-Sigma-Delta-Modulation for Area- and Power-Efficient A/D Conversion with Low Jitter Sensitivity", diss. Sebastian Zeller, Erlangen; "A High Speed/High Linearity Continuous-Time Delta-Sigma Modulator", diss. Chao Chu, University of Ulm).

DSADC ICs are using complicated differential signal processing (and perfect layout) in combination with switched capacitor technology (SCT), so that parasitic coupling e.g. over the substrate - in the ideal case - is canceled. However, SCT is always limited by the kT/C-noise, and in combination with IC technology constraints there is a fundamental noise limit for SCT-DSADCs. Therefore, in recent years new designs were presented which use a SAR-ADC with digital filtering in order to yield a step forward, e.g. the according LTC23xx family.

It is very interesting that there is a remarkable convergence of circuit techniques while coming from the MS- and DS-method sides. The basic differences between the MS- and my DS-approach (started 1 year ago) are:
-  in order to obtain up to 1000 meas./s, the switch PWM frequency is 200 kHz. A fixed PWM frequency is required for a 200:1 overampling ratio. For lower meas. rate and improved linearity, a modified pulse density scheme could be applied (I already used that successfully in an older DS design).
-  the first integrator is a composite design: a very fast discrete JFET amplifier is corrected by a slow, but dc precise JFET-OP. The 2 gains are combined smoothly without causing steep phase slopes or peaks. LTSpice says that the gain is 162 dB at 10Hz, 67dB at 100 kHz, gbp is 68MHz at 1MHz, the transient response to 125uA current pulses is a <250uV <30ns peak at ni-input (I'm curious to test the real PCB). This high bandwidth (or fast settling time) is essential to obtain mean reference currents independent on duty cycle (a weak point of this topology).

I think it makes good sense to develop 2 different designs and to learn from differences. It will take still several months until I can report here.

[Kleinstein]

A 250 µV and 30 ns pulse at the integrator input sounds really good.
The pulses I see in real hardware and also in the simulation are quite a bit longer (e.g. 200 ns range) and also a bit higher - they are visible at the scope (though using more current (550 µA step) and looking at an intermediate test point with some gain). As long as the switching frequency is fixed there is not much effect. It gets even better when the number of short pulses is well behaved (e.g. about proportional to the voltage). So I think the importance of the integrator speed can be a bit lower than often though.
It also makes a difference if switching is at the integrator input (as I have it) or at the reference side (as many DS ADCs, e.g. the ADC in the KS 3446x). Switching at the integrator adds some extra charge injection pulse and also adds to the capacitance. So the switching pulse is expected to be a little worse, but there are other advantages (e.g better compensation of switch resistance, no need for ref buffering).

200 kHz switching does not sound very fast for the DS ADC. My upper limit is at some 300 kHz, but I prefer slower as long as the DA effect is not yet an issue.

I think the switched capacitor technique has not only the problem with kt/c - that is only slightly worse than the resistor noise in a contineous time integrator.  The SCT also has nonlinear resistance of the MOS switches.  In the calculated noise the resistors are often the largest noise sources. So the kT/C noise part is expected to be similar an important part of the noise. Larger capacitors also need more area and thus cost. Still the chips got quite good with the AD7177. Noise wise it is impressive.
The other point is that the SCT technique has very low offset drift and thus does not need an extra auto-zero switching. With continuous integration this at least gets a bit challenging.  One can use a zero drift OP in the integrator, but there are other source of offset drift (e.g. the resistors).

I think it makes good sense to develop 2 different designs and to learn from differences.

Having 2 "designs" and look at the differences is a nice way to look at INL effects. Already just slightly different modulation is enough to move nonlinear effects to a different voltage and thus create a visible difference from 2 reading with essentially the same HW, but lightly different control. It is a nice and simple (no need for an expensive super linear calibrator) test for my MS design. Chances are this could also work with a DS design, if there is room in the FPGA. Compared to classic INL tests this can be fast and quite sensitive, though not catching all.

[DeltaSigmaD]

To obtain a higher measurement rate you have to apply a PWM feedback in order to get "many bits each pulse". But if you have a PWM, the switching frequency is limited by the extreme values of the duty cycles which can be allowed for acceptable linearity error. For instance, if you want to have a ADC working range of 15% to 85% of reference voltage range, then you have pulse widths from 750ns to 4.25us with 200kHz PWM frequency. The settling into the ppm range after switching must be completed within these 750ns, otherwise you can forget linearity. I gained experience with this difficult demand. Also if a pulse density method is applied, you must maintain a pulse pause larger than the settling time to a few ppm. A suitable scheme is here for instance >=2us pulse pause for 2us pulse width.

Just today I found that I missed the introduction of the switch TMUX1133 of Texas Instr. (2019). Assuming that I understand the datasheet correctly, this SPDT would be excellent for DS-ADCs - with the exception of the reference voltage limitation to +/-2.5V. This part seems to include a much faster unipolar-->bipolar digital level translation than with 74HC4053. I'm afraid that I have to redesign of my PCB layout to paste this new IC into the ADC circuit hoping that it is worth for the additional work. Unfortunately, the tight dynamic demands exclude alternative switches in the layout (there are no packages common to 74LV4053 and TMUX1133).

[iMo]

Would be great to create a detailed description of the "MS switching algorithm" of the latest design.
My current understanding is an fpga verilog source for it would be something like 200 lines of code with an SPI interface.
It may even fit into a smallest fpga, like ice40lp384.
That may help with experiments..

PS: Jaromir's MS he published in past is 300 lines verilog long inclusive an uart interface (I would prefer SPI one).

[Kleinstein]

My latest version has 3 different run-up versions to choose. The basic one (AFAIK also used similar by Jaromir and in the 34401) is really simple, but still good:
  each period of the run-up has 3 phases:
 1) a phase with the positive reference (e.g. 1 µs)
 2) a phase with a ref. Setting that depends on a single comparator reading (e.g. some 8 µs)
 3) a phase with the negative reference (e.g. 1 µs)
So there are only 2 cases. The time for the comparator reading is a possible parameter, typically at the start of the positive phase. Depending on the integrator speed the short fixed phases can be shorter (e.g. 500 ns for my fastest version). The number of short pulse linear follows the input voltage and this makes it quite forgiving to incomplete settling.

Another version has a 4th phase also depending on another comparator reading. This version is however not as good as settling is more critical.
There is even an old patent (US5200752) on this idea - but it is not really working well. I have kept it only for test purposes.
 
The 3rd version has a slight modification at the transitions. So there is no direct step from positive to negative, but a short (e.g. 500 ns) phase with zero reference in between. The idea here is to reduce the effect of clock jitter and that 2 smaller steps may be less disrupting than 1 large step. As the sequence is fixed, the short zero phase does not need full settling, so the time could be quite fast (like 100 ns). It probably depends on the HW details if this works better or worse.

The more PWM like feedback is a different alternative - I have not tested this, as there is more effort for the feedback control. For the MS ADC the switching frequency can be lower, especially if the feedback control is good. The requirements on settling is higher and thus longer minimum pulse width. So the maximum modulation frequency is also lower.  I would consider PWM like control with some 10 kHz as an alternative to the 2 pattern type modulation with some 100 kHz. With the lower frequency there is more time for settling (e.g. 5-10 µs), but also much closer settling needed. The 3 phase type modulation wants something like 1% settling after 1 µs, while the PWM like method wants some 0.01% so it may need some 5 µs.

The more accurate FB is however demanding for the AVR and programming a complicated math heavy algorithm in ASM (with constant run-time constraints) is tricky. It can be an option for my new version with a more powerful µC with code in C.

The run-down part is for the first part similar to other many MS ADCs:
It starts with the stronger (positive) reference about 300 ns past zero crossing (or a minimum length if the comparator already is the right sign).
The next step is the negative reference, a little past zero corssing.
The 3 rd part is the slow slope with both reference combined, again till zero crossing of the comparator.
Than comes some waiting time with the references off (e.g. 96 µs from start of rundown) and the µC internal ADC is started to sample the residual charge for some 10 µs followed by the actual conversion ( ~ 50 µs).
I currently use an extra ADC reading for the average voltage (not directly relevant for the result) and than a separate ADC reading for the start charge before the start of the next conversion. For fast modes a single residual charge reading could be used for the end and start of the next conversion.

IN addition to the actual conversion one would also need the extra loops for the measurement of the slow slope/reference ratio (still relatively easy) and the auxiliary ADC scale factor (a bit more tricky). So my ADC version with the auxiliary ADC may be a bít longer to implement in a FPGA. It would also need an extra external ADC.

[Kleinstein]

Just today I found that I missed the introduction of the switch TMUX1133 of Texas Instr. (2019). Assuming that I understand the datasheet correctly, this SPDT would be excellent for DS-ADCs - with the exception of the reference voltage limitation to +/-2.5V. This part seems to include a much faster unipolar-->bipolar digital level translation than with 74HC4053. I'm afraid that I have to redesign of my PCB layout to paste this new IC into the ADC circuit hoping that it is worth for the additional work. Unfortunately, the tight dynamic demands exclude alternative switches in the layout (there are no packages common to 74LV4053 and TMUX1133).

Both the LV4053 and TMUX1133 are limitd to low voltage. So they are OK for switches at the intgrator input, but would limit the ref. voltage to some +-2.5 V. With a low ref voltage settling and the integrator noise get more important. The S/N ratio for the resistor contribution scales with the power - so one would also need a higher current to get the same noise level.  A higher voltage really makes it easier on the amplifiers: less sensitive to noise, less current and less critical settling level.  The downside of switching at the intgrator side is that there is additional kt/c noise from the gate charge. This can be a problem with very fast modulation. So switching on the voltage side gets more attractive with very fast modulation.

I found the LV4053 sufficient low resistance for the 280 µA current level I use, so no real need for even lower R_on. It may be requited if a 2.5 V ref is set and a higher current (e.g. 1 mA) is used.

[iMo]

.. Both the LV4053 and TMUX1133 are limitd to low voltage. So they are OK for switches at the intgrator input, but would limit the ref. voltage to some +-2.5 V. With a low ref voltage settling and the integrator noise get more important. The S/N ratio for the resistor contribution scales with the power - so one would also need a higher current to get the same noise level.  A higher voltage really makes it easier on the amplifiers: less sensitive to noise, less current and less critical settling level.  The downside of switching at the intgrator side is that there is additional kt/c noise from the gate charge. This can be a problem with very fast modulation. So switching on the voltage side gets more attractive with very fast modulation.

I found the LV4053 sufficient low resistance for the 280 µA current level I use, so no real need for even lower R_on. It may be requited if a 2.5 V ref is set and a higher current (e.g. 1 mA) is used.

Imagine a +-5V design, with +-2.5V reference (and 3.3V fpga/mcu logic). What resolution MS would you expect is doable then?

[Kleinstein]

With a +-2.5 V reference I would think of reducing the resistors at the integrator by about a factor of 10 compared to the +-14 V ref case. So maybe 5 K resistors and thus 500 µA reference current.  The resistor noise would go down by a factor of about 3. The noise from the integrator does not get lower and thus gets more important. So overall noise may be lower by a factor of 2, while the ranges is reduces by a factor of 5 to 6.  So the reduction in the voltage would cost a little more than 1 bit in the SNR if slightly worse INL is accepted. If the integrator current is not increased much there is a little more loss in the SNR.  So I would expect something like a 200 nV_rms noise level for the difference of 2 conversions of 20 ms as the noise limit.

The quantization limit could still be very low (e.g. 28 bit level at 20 ms), but less integrator swing would still mean a larger cap and thus more noise for the residual charge. So the cross over where the limit is from the residual charge would move a little to longer integration times (e.g. 2 ms instead of 1 ms).

[dietert1]

My latest version has 3 different run-up versions to choose. The basic one (AFAIK also used similar by Jaromir and in the 34401) is really simple, but still good:
  each period of the run-up has 3 phases:
 1) a phase with the positive reference (e.g. 1 µs)
 2) a phase with a ref. Setting that depends on a single comparator reading (e.g. some 8 µs)
 3) a phase with the negative reference (e.g. 1 µs)
So there are only 2 cases. ...

As far as i understand this is the description of a PWM DAC running at 100 KHz and with only two pulse widths (10% and 90 %). It is made into an ADC by a sigma-delta type control loop that lets it follow the input signal.
Why does it have to be 100 KHz? PWMs in calibrators usually run at much lower frequencies, like 1 KHz or even below. In the Solartron mark and space scheme it seemed to be about 200 Hz and the PWM is using more different pulse widths to be a little more "agile".

Regards, Dieter

[Kleinstein]

The feedback at the integrator is kind of like a 1st order sigma delta converter. So look at the integratgor output and than decide between the 2 cases of e.g. 10% and 90% PWM.

The frequency does not have to be 100 kHz - this number is just an example and roughtly to order of magnitude. Different meters use different frequencies in multi-slope and related converters.  The Solartron and related are at the slow end with some 1 kHz and even a bit below. The Advantest 6581 is also quite slow with some 5 kHz (in slow mode). The Prema custom SD ADC is also relatively slow modulation. AFAIR the Keithlthey 2000 and similar run at some 25 kHz. The 34401 and 3458 use some 330 kHz and the 3446x even more.

The frequency for the modulation is a compromise:  The run-down get longer with a slow modulation as the worst case charge is larger. A slower run-down also means the slow slope gets more important. The noise in the measurement of the final charge gets higher with slow modulation as this requires a larger capacitor and thus less votlage for the same charge. Another factor favoring a high frequency is the error from DA : the more charge is stored in the cap, the larger the DA related error. Fast modulation is kind of the brute force way against DA.

On the other side a fast modulation also produces disadvantages: it needs a faster integrator to allow relative short minimal pulse length. The error from Integrator settling and similar switching related erros gets more important as more cycels sum up. Similar more cycle increases noise from jitter more impartant (scales about with the square root of the frequency).

So far I have tried a frequency from some 20 kHz to 350 kHz. The best choice depends on the integration time: shorter conversion are more sensitive to the final charge noise campared to jitter and a quick rundown is also impartant than.
At 1 PLC, noise wise the best freuquency is relatively low, maybe in the 10 kHz range. At least 40 kHz work a little better than 80 kHz. For the INL error it is hard to tell and I have not tested very much with the lower frequencies. There is a hope to reduce the coupling effects and it does no yet look like there is much DA effect (the good capacitor helps). For improving in the errors it helps to use not the best case first - it is allready hard to measure the INL.


For rather slow modulation more than just the simple feedback can help to reduce the DA error. The Solartron and similar ADCs use a more contiuous PWM and this gives less (my estimate is about 4 x) charge with the same frequency.
The 34401 and similar continuous integrating ADCs need the high frequency also to get enough resolution for 1 PLC conversions. At 1 PLC it is quatization limited as the auxilary ADC is only 10 Bit (though fast). I think the main driving part for the fast modulation in this case was the quatization limit.

The relatively fast simple feedback is about as simple as it gets - after all the whole ADC started as a simple MS-ADC - at least form the HW side it still is simple. There are a few good perfoming parts (OPA1641, LV4053 switches, TDK C0G cap and ORN resistor arrays), but these are not especially expensive. It only later turned out that the simple ADC is also very low noise.

[Kleinstein]

A short update:

I got the main part of the STM32 based ADC version running. So it looks like the hardware is working like planed. Despite the slightly faster µC the rundown seems to be a little slower, as the comparator in the µc is a bit slow. The software still needs some polish and the part to measure the slow slope and ADC scale.
The software is not yet putting the result together, but this is the relatively easy / predictable part. So I have not yet tested the noise and linearity.


The ADC principle is still the same as with the AVR based version, but the µC and software is different: The AVR version uses program run time and thus ASM code for the timing and was thus not so easy to program. Control of the voltmeter input section is possible, but limited (e.g. 1 byte commands).

The new ARM based version uses more support from the µC internal timer hardware, with a trigger signal from the comparator to the timer and between timers.
As the critical timing is in hardware, the program can be more flexible C code. The hardware control for the ADC is a bit tricky, but the extra parts (communication and input control) are much easier.

The board shown on the photo has the ADC and a voltmeter input stage.
The actual ADC is the part about 50x50 mm down and left from the µC.
The lower left corner is the reference and reference amplification. For the test phase it is still only a LM329, but an upgrade is easy.
The central part with the PTF65/ PTF56 resistors is the main amplifier.
3 of the SO16 chips are for input switching (including parts for 4 wire ohms).
The 4 THT fets are for input protection and switching for the 2 inputs.
The relay is still not soldered in, just there for the picture - it is better to wash the board without the relay.


As there were some questions about the run-up modulation, here is the code for it. It is run inside a an interrupt service routine triggered about half way through the PWM cycle, the exact time does not matter.

Code: [Select]

if (ru_count)
{                                  // normal ru-up step
  if ((COMP2->CSR & COMP_CSR_COMP2VALUE))    // test comparator
  {
TIM2->CCR1 = ru_high;          // PWM registers for the references: positive is active at the end, negative is active at start
TIM2->CCR2 = ru_high;          // switch late -> more negative ref. , uses preload: effective only for next period
  }
  else
  {
TIM2->CCR1 = ru_low;           // switch early on both, more positive phase
TIM2->CCR2 = ru_low;
    ru_sum++;                      // count number of positive phases
  }
  ru_count--;
}
else
 .....   // run-down part


[dietert1]

Recently i thought a little about that single bit SD runup phase you use. If i understand right multi-bit SD means using more than two different PWM settings. I think that terminology is about the details of the time division scheme, while the hardware still remains a single bit DAC. Using a multi-bit PWM scheme can reduce the PWM frequency. Avoiding superfluous switching reduces noise and errors.

In order to implement that one would need a link from the ADC input to one of the MCU ADC inputs, probably with a divider to match the input ranges. Isn't that something easy to do? Everything else would be in the firmware. The first step the firmware needs to learn is determine the AC content of the input signal.

Regards, Dieter

[Kleinstein]

Yes the way of multi bit feedback (e.g. auxiliary ADC to read the charge and than adjust the PWM ratio of the feedback) is a possibly way. For the STM32 version there is a suitable divider on the board.   This can use a lower frequency and also has to use a lower frequency: the distance between swiching changes and the intergrator really has to be settled before the next switching happens. The run-up periods will usually have a very similar PWM ratio and errors would add up for the periods.

On the other side the simple 2 pattern feedback has only discrete cases for the time between switching and in the simple form the number of critical short phases is essentially (as far as it works with integer numbers) proprotional to the input voltage. So an error would be mainly an error in the gain. The INL error would not add up.

The ideal case (DC signal) residual charge can be pretty small, but the worst case charge can be quite large. An input signal with lots of AC can upset the feedback quite a bit (e.g. worst case jump just after the last reading to adjust PWM). So the worst case run-down would also be slow, even though the average rundown could be OK.

It is relatively easy to implement - though not so easy in ASM with the additional need for a fixed runtime (my AVR version). In C and HW assisted run-down the software is also easy.

I see no real need to look at the AC contend - one can't do much about the worst case anyway .  The system is fixed (asuming the input signal as DC) and this only needs to be tuned once to get a well stable feedback. Quite a lot of this could be done in theory - so just get the math right. The problem would be a bit similar to a PLL.

With the current setup one can also lower the frequency of the 1 bit feedback far enough (e.g. 40 kHz) to have jitter as only a smaller part of the noise. So the possible improvement in the noise is limited (maybe 10-20%). It would be mainly for the INL.

[dietert1]

Yes this is about gain stability. I think i know how to make an 8 digit stable PWM at 10 KHz, but not at 100 KHz.  I mean a DVM with 7 or 8 digit capability in terms of noise should also have a reference of similar quality and an ADC with stable gain.
As far as i understand, worst case would be an unexpected large input voltage change. Shouldn't there be a lowpass filter? The idea of sampling the input voltage at enough bandwidth would be to capture rapid input change and select a proper next PWM bit to avoid large integrator swing.
Anyway my idea would be that good linearity and gain precision is required for measurements with low AC content, lets say < 1 %, while other measurements with more AC could be a bit more rough. I am pretty much convinced Keysight and others are cheating there, too. Maybe i can test it with the R6581T.

Regards, Dieter

[Kleinstein]

The KS meters ( 34401, 3458, 3446x use pretty fast beedback, of > 300kHz). AFAIK there is a little filtering at the input (maybe 1 K sereis resistance and some 100 pF or a bit more) so this would be only a little fitlering. The way the AZ switching is done does not allow for much filtering, as the ADC must be quite fast with starting integration. The 3446x use the same ADC also for the digital RMS, so the use with AC is well tested and not only by accident.

The R6581 is using slow feedback, but AFAIR also not much filtering, a little more when the extra cap is enabled.
The negative effect would be mainly a slightly larger worst case charge and this slower rundown The run-down part is quite slow anyway with the R6581.  The solartron meter may react with higher linearity error if there is added AC, as the integration time may not be a nominal with more AC and this can even happen with mains harmonics normally well surpressed.
Normally one has a low AC contend with precision measurements. The mains hum suppression is usually limited - a mains PLL is tricky and easily adds jitter noise. I have some idea to improve mains hum suppresion even without PLL, but this gets a bit off topic. Some AC background may also act as dithering to reduce the effect of idle tones - so some AC may even improve the INL / DNL.

A few meters have an extra low pass filter, at the input (e.g. the DA1281). The older fluke ones need it because of there odd ADC (recicculating remainder and thus a sampling ADC with relatively little oversampling). A filter at the very input is tricky, as th source impedane has an effect and settling gets slow. A fitler behind an initial amplifier / buffer (e.g. like Keithly 200x, Datron 1281) could be nice, but I only know of one in the K2182.
I have a little input filtering planed as an option, but not much (maybe comparable to the R6581). A larger cap is however possible.

The ADC gain is pretty stable - the small extra settling effect is only a small correction and the settling does not change that much. The main factor for gain stability is the resistor ratio in the arrays - so far a got about 1 ppm/K for the 2 AVR based version and expect a similar one for the new one. With the NOMCA or separate resistors there was some 1/f noise is the gain - kind of random variations in the resistance, like the resistor excess noise.

The new PCB connector for the reference can have a lower noise one later.
A high ADC resolution (7-8 digit) can also have some advantage with only a LM399 ref.: At 1/10 the full scale the demand on the ref. is lower than at full scale and a good ADC still helps.  Another point is that a good ADC enables to use some ACAL way to measure the amplifier / divider gain. If the extra ADC resolution does not come at much extra costs, this could be an option even for a lower cost DMM. For a DIY solution it is also interesting as it can simplify the gain calibration. With low noise of the ADC but a drifting ADC gain, there is the option to do a gain cal step for every conversion: the Keithley K19x do it this way. I can see an improvement when poor quality resistors are used.

[dietert1]

You know the 3458A uses proprietary parts to implement the high PWM frequency. Don't know whether a 4053 of whatever make can compete. Concerning precision with AC presence, when i think about it once more, it's an undefined corner anyway. As you write, with asynchronous AC and integration the result will be more or less random at a % level. So one could just watch out the integrator doesn't clip and forget about nonlinearity due to dielectric absorption.

Thanks again for your comments, i guess after finishing that PWM calibrator with a redundant LM399 14 V reference, i may try some supplement to make it into an ADC. Hope it doesn't take forever.

Regards, Dieter

[Kleinstein]

The LV4053 switches perform quite well.  With a good quality capacitor, and / or a better FB algorithm the error from DA is not large and one does not need such a high switching frequency. A lower switching frequency reduces the demand on the switches a little, when it comes to jitter and charge injection. The main downside is a slightly longer time for run-down. This would be an issue for high speed (e.g. > 1 kSPS), but not a 1 PLC.

The resistance of the Ti 74LV4053 is low enough to get low square contribution (see some earlier posts in ths thread) even without an extra driven substrate like in the 3458. The jitter is at an ecceptabe level, especially with a slightly slower modulation. A jitter contribution to the noise is visible, but it is not dominant at 100 kHz. I can still reach a noise level a little lower than the 3458.

The HP3458 needs special switches as there are different resistors for the input, refrence and the small slope. However the small slope, is not so critical with the resistance and could get away without a matched restance.   I consider the choice of different resistors (40 K and 50 K) an odd point in the 3458 desig.  3x50 K and +-14 V instead of +-12 V ref would be better in essentially all aspects. Equal resistors for the ref and input are the obvious choice when using of the shelf resistor arrays and they allow to use 3 equal switches for the main ADC switching.

[iMo]

.. The board shown on the photo has the ADC and a voltmeter input stage.

The board is nice but already more complex (number of parts) than my 34401, it seems..   
What is the transformer upper left?
PS: do you plan to put the sw on the Github (for example)?

[Kleinstein]

The upper left corner is an isolated DCDC converter. The PCB was made for an SN6505B, but this was not available. So I switched to the SN6505A with a lower switching frequency and this needs a slightly larger transformer than originally planed for. Chances are the transformer could be smaller, but this was what I had at hand.

The input part is a bit more complicated.  This starts with using bootstapped supply to the amplifiers to ensure good linearity. The extra part to get a +-20(25) V input range also adds a bit complication.

Just counting the chips is also a bit misleading with the 34401: it has a special input hybrid for the input switching, that replaces several chips if done with standard parts.

The ADC part is acturally quite similar to the 34401:  4053 switching, 74AC74 for synchronization, the 2 OP integrator and using the µC internal ADC for measuring the residual charge. I don't need the extra ASIC, but 2 OPs instead.

I will likely put the SW on github or similar, but that part is not yet finshed.  I just got it sending out the raw data via UART.  The part to measure the slow slope and ADC scale and the control for an AZ cycle are still missing.