I did a little more INL testing on the ARM based ADC / DVM. The turn over and sum of 2 voltages test got a little automated. The DVM switches a sequence of 4 settings with 2 high side inputs and 2 low side inputs, to get all 4 combination in a sequence (16 x 16 PLC readings each). For most of the points I still looked at the data by hand, to find phases with low noise. The problem is especially popcorn noise from the references (external and in ternal LM399 based). There are low noise phases and higher noise phases. Brute force averaging needs quite some time to get to the level of quite phases. May have to teach the computer to see quite phases and do a smarter average.

For the more long range linearity (soft INL) I now have 3 tests:

1) the classic turn over test with the same external voltage read positive and negative. The sequence includes 2 additional zeros.

2) read the sum of 2 voltages that make up some 9.4 V from my reference. The 2 voltages are derived from a single LM399 with a amplifier, divider and buffer as used before.

3) use an external voltage source and read the same voltage in a classical AZ mode (0 and the voltage) and in my differential mode, where the ADC reads -1/2 U and + 1/2 U. The 2 voltages are not exactly opposite, but the difference should be accurate as only the ground shifts. So this is a little like the case 2, but with one voltage measured negative and fixed at half the voltage. For the DVM this is measuring the same voltage in the 10 V and 20 V range.

Attached are the results for the 3 tests.

The result of the turn over test is odd: it is more like linear, while the expected form is quadratic. I currently have no real idea what mechanism to give a slightly different gain for the positive and negative side. The main expected effect from the nonlinear on-resistance of the CMOS switch is square law.

The result for the sum of 2 voltages does not looks so bad, especially for the negative side. The positive side shows a little more error, but still not too bad with some 4.5 µV in the center. With the scattering it is a bit hard to tell if the curve follows the expected parabola form for the positive side - it at least looks a bit like it.

The test with the 10 and 20 V range gives some kind of v³ contribution, a bit like expected for the self heating of the resistors at the integrator input. The difference gets quite large - I had hoped for better performance. The difference is also larger than one would expect from the INL seen in the test with half the voltage (but with the same sign and with a different sequence).

The ACAL procedure also gives a slight hint on linearity, though this also includes the amplifier and possible nonlinear effects at the amplifier, especially the feedback resistors. The results for a positive and negative test voltage are reasonably close (-0.2 ppm , -1.8 ppm and -0.6 ppm for the positive side for gain 7, gain 100/ gain 7.4 and the divider), but still a tendency to have lower results for the positive side.