"NU180" - A U180 drop-in replacement for the 3458A.

[IanJ]

What are people's opinions about potential performance degradation when moving precision surface-mount resistors between boards? Anyway, I'm probably going to order a second set.

Be careful you don't damage them with too much heat when desoldering. Helps to clean them top and bottom with IPA before re-fitting so that you keep trapped flux to a minimum.

PS. No idea what resistors you are using, but I used to use these 2ppm/degC ones a lot!
https://uk.farnell.com/c/passive-components/resistors-fixed-value/chip-smd-resistors?brand=holsworthy-te-connectivity&product-range=ru73-series
https://uk.farnell.com/c/passive-components/resistors-fixed-value/chip-smd-resistors?brand=te-connectivity&product-range=ru73x-series

Ian.

[Zondar]

Oh, sorry, I was looking at MiDi's schematic (obviously different). I can't see why that node should cause problems. Can you please attach your whole schematic? Thanks.

The resistors are Vishay's FSRM foil, 0.01%, 0.2 ppm TCR.

[wanghar]

Zondar, it's this: https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6061031/#msg6061031

[Kleinstein]

The exact value of the 12 V,-12V and 5 V should not matter. The ratio is more relevant, especially the +12 V to -12 V ratio. The -12 to 5 V ratio sets the ratio for the small reference steps and via the 604 K and ladder part the zero from the ladder part.
There are still limits for the absolute values (so the 6.6 V ADR1001 needs a change to get accepted). A deviation in the 7 to 12 V gain step would act like a different ref. voltage.

I would not expect so much resistor drift to cause so much ratio error to cause the error message. The low TC resistors are mainly to get a low gain TC and for the 50 K also to have good linearity of the resistor itself.
The lower grade resistors should still be good enough to make the ADC work, only with a higher gain TC and maybe slightly higher DNL error.

A somewhat borderline point could be a higher supply for the PLD compared to the switches. It may be worth testing the switches with VDD = 5 V like the PLD and maybe VSS = GND or only -300 mV with an extra schottky diode to GND.

Another possible issue could be the switch capacitance. The are overall 13 switches connected to the integrator. With 11 pF each for the off state this would be some 143 pF and most of the time 3 switches on would add another 70 pF. This is likely considerably more (like 2 x) than the original U180 and may cause a bit more ringing with the integrator. Reducing C128 could compensate to some degree (still at the other side of the ferrites).

For the final testing one would really need a GPIB interface. A 3458 without PC link makes relatively little sense.

If one gets the ADC working, it may be worth looking at the DNL from the slope ratios. The DNL error would be largest with short integration, but still via the slow path. So some 1 ms (maybe 0.2 ms) and non AZ mode to avoid complications from drift in the zero reading.

[Zondar]

Thanks for the reminder wanghar. Aside from the switch modulation, it seems essentially identical to mine.

My +12/-12 ratio is within 0.02%. Is that adequate or should it be better?

There is no difference in supply voltage between the CPLD and the switches. Both are Vdd = 5V. I had considered using Vdd2 (~4.6V) as generally used for the switches in U180, but I felt it was safer to leave both at 5V. The negative supply for the switches is GND2 ~= -0.4.

I don't suppose there's an actual measurement for U180's switch node capacitance?

I did test the switches (alone) at Vss=0V, with no notable difference in basic performance. Philosophically, I still prefer using GND2 for Vss.

For GPIB, is the KS/Agilent one necessary (these are either very expensive or counterfeit or both), or are they all the same? The presumably-counterfeit ones can be quite cheap (~$60 or so), but I was considering getting the Siglent one, since that is priced semi-OK (~$170) for one that is guaranteed to not be counterfeit.

Or maybe get the Prologix ethernet adapter? Expensive, but it should maximize compatibility between OS's, etc. There's also an open-source design out there.

[hp3310a]

There are almost no meaningful differences between your board and mine.

If the hardware is the same, maybe it's a software problem?

[iMo]

Also i would be tempted to generate the bitstream for the cpld with a different sw chain/hdl, if available.
Especially those PD settings, slew rates settings, pin keeper settings may cause some issues too.
So you may split the debugging into two areas - the analog part (resistors, capacitancies, voltages/currents), and the digital part (functionality - like the proper sequences, speeds/prop_delays, signal's voltage levels), for example..

[Zondar]

All 3 designs are substantially the same and I expect use the same quite minimal CPLD code. There isn't much to change in the code.

My version of CPLD is the 7.5ns AS (non-L) version, and it looks like wanghar used the same. I used 33 Ohm series resistors on output lines, whereas wanghar used 22 Ohm (shouldn't matter).

I used ADG734's whereas wanghar used ADG788's, but these appear to be the same chips with the same specs, just in different packages.

Wanghar included switch modulation whereas I left that out, but he hasn't discussed that aside from a claim that it shouldn't matter for these tests. I'd be curious to hear if and how much "modulation" is occurring.

Judging from the op-amp daughter-board, etc., I think wanghar's 3458A and mine are the same or close to the same version. That might not matter too much regarding U180 in any event, which as far as I'm aware was never redesigned.

The best explanation I have, which is of no real help, is that subtle differences in resistances or other small factors are important and may even have to be tuned to the system its in.

I'm probably going to order a second set of precision resistors. A question here is whether the "mathematical" values are preferred (e.g. 16,666.7 Ohms), or should be slightly different to account for other circuitry on the A3 board. Also, how is the "4.14k" resistor calculated?

I am anxious to hear about MiDi's board, as his experience may help shed more light on things too. I hope he's making progress on it.

[iMo]

For example you may capture specific events during the analog conversion on the U180 and compare them to the same capture on your NU180. Not the analog signals, but the digital signals. To be confident the cpld logic works the same (plus minus couple of ns). A four channel 100MHz scope may be enough for that (or better use an LA).
So a structured focused step by step debugging (with a plan)..

[Kleinstein]

There is not much software involved. The AFT150x programming follows the same logic (there could still be swapped pins depending on the layout). The rundown part does the switching via the HC14 gates and not U180. So for this part the swith part should not change much. Also the intergrator settling should not be that bad, as the small rundown steps produce on the relatively litte disturbance and thus low amplitude for possible ringing.

A difference between boards can come from small differences in the actual resistor values. Also PCB stress can effect the resistors a little. The boards seem to be right at the edge for triggering an error, both in the self test and use.

A possible weak spot can be the socket with contakt resistance on some pins. This may also change with temperature / time.
For the ground part one could try using additional pins in paralelel. AFAIK many of the unused pins of U180 are connected to GND.

0.02% symmetry for the +-12 V references should be well good enough. The issue may be more with the symmetry of the two 80 K resistors that are likely active also during run-down and maybe the switches. With the boards the positive and negative side use separate chips. With the relatively small R_on this should not be that bad.

The 4.14 K and 6 K are made to get 12 V from 7 V ref. in. The exact value should not matter very much, as the LTZ1000 refs are not all the same.
For the 16.x K the math wants 16.6666 K minus the R_out of the HC14. This would be some 16.6 K. The part on the A3 board seems to be a bit higher resistance, but this should not be that relevant as those resistors at the far end of the ladder have less effect (see the simulation of wanghar). The small difference in the simulation is from 604 K instead of ideal 600 K for the offset part.

With multiple boards showing similar issues (just ad the edge of working) there may be more than just the resistor tolerances to be wrong.
Not having the case closed may give occasional errors from hum or similar interference.

Some plans have some control inputs open at the switches - this would be a possible issue.

The supply modulation should be small. Some 0.3 mA times some 4 ohms for the drop and half of that as the supply change. So only some +-6 mV change.

[MiDi]

When looking into the generated .fit file from WinCupl, the default is Pin_keep_mode = ON & Output_fast = OFF (see attached code).
To change the default, the following lines need to be inserted before any assignments in the PLD file:
PROPERTY ATMEL { OUTPUT_FAST = ON };
PROPERTY ATMEL { PIN_KEEP = OFF };

Have you checked if there is any difference between fast/slow slew rate?
Would not expect any difference with PIN_KEEP turned off.

Code: [Select]

Atmel ATF1502AS Fitter Version 1.8.7.8 ,running Thu Oct 23 21:18:45 2025


fit1502 C:\WINCUPL\U180.tt2 -CUPL -dev P1502T44 -JTAG ON


****** Initial fitting strategy and property ******
 Pla_in_file = U180.tt2
 Pla_out_file = U180.tt3
 Jedec_file = U180.jed
 Vector_file = U180.tmv
 verilog_file = U180.vt
 Time_file =
 Log_file = U180.fit
 err_file =
 Device_name = TQFP44
 Module_name =
 Package_type = TQFP
 Preassign_file =
 Property_file =
 Sleep_mode =
 Preassignment =
 Security_mode = OFF
 Pin_keep_mode = ON
 Dedicated_input_clock =
 Dedicated_input_reset =
 Dedicated_input_oe =
 supporter = CUPL
 optimize = ON
 Soft_buffer =
 Xor_synthesis = OFF
 Foldback_logic =  on
 Expander =
 Cascade_logic = OFF
 Dedicated_input =
 Output_fast = OFF
 *******************************
 Power down pin 1 = OFF
 Power down pin 2 = OFF
 power_reset = OFF
 JTAG = ON
 TDI pullup = OFF
 TMS pullup = OFF
 MC_power = OFF
 Open_collector = OFF
 ITD0 = ON
 ITD1 = ON
 ITD2 = ON
 Fast_inlatch = off
 *******************************
---------------------------------------------------------
 Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF
 ...

Performing global Output Enable pin assignments ...

Performing global pin assignments ...
--------------------------------------



Final global control pins assignment (if applicable)...
-------------------------------------------------------
CLK assigned to pin  37



Performing input pin pre-assignments ...
------------------------------------
CLK assigned to pin  37

Attempt to place floating signals ...
------------------------------------
TDI is placed at pin 1 (MC 4)
TMS is placed at pin 7 (MC 9)
PR1 is placed at pin 10 (MC 11)
PS1 is placed at pin 11 (MC 12)
NS1 is placed at pin 12 (MC 13)
NR1 is placed at pin 13 (MC 14)
RUSN2 is placed at pin 14 (MC 15)
LADSN is placed at pin 15 (MC 16)
RUSN1 is placed at pin 35 (MC 17)
RUSN3 is placed at pin 34 (MC 18)
SLA is placed at pin 33 (MC 19)
TDO is placed at pin 32 (MC 20)
SLB is placed at pin 31 (MC 21)
RUZ is placed at pin 30 (MC 22)
RUS is placed at pin 28 (MC 23)
ENS is placed at pin 27 (MC 24)
TCK is placed at pin 26 (MC 25)
RUR is placed at pin 25 (MC 26)
ENR is placed at pin 23 (MC 27)
NR2 is placed at pin 22 (MC 28)
NS2 is placed at pin 21 (MC 29)
ZERO is placed at pin 20 (MC 30)
PS2 is placed at pin 19 (MC 31)
PR2 is placed at pin 18 (MC 32)

                                                                 
                                                                 
                                                                 
                                                                 
                                            R  R                 
                                            U  U                 
                          V           C  G  S  S                 
                          C           L  N  N  N                 
                          C           K  D  1  3                 
               ____________________________________             
              /  44 43 42 41 40 39 38 37 36 35 34  \             
         TDI |  1                                33 | SLA       
             |  2                                32 | TDO       
             |  3                                31 | SLB       
         GND |  4                                30 | RUZ       
             |  5                                29 | VCC       
             |  6            ATF1502             28 | RUS       
         TMS |  7          44-Lead TQFP          27 | ENS       
             |  8                                26 | TCK       
         VCC |  9                                25 | RUR       
         PR1 | 10                                24 | GND       
         PS1 | 11                                23 | ENR       
             |   12 13 14 15 16 17 18 19 20 21 22   |           
              \____________________________________/             
                 N  N  R  L  G  V  P  P  Z  N  N                 
                 S  R  U  A  N  C  R  S  E  S  R                 
                 1  1  S  D  D  C  2  2  R  2  2                 
                       N  S              O                       
                       2  N                                     



VCC = Supply Voltage pin which must be connected to (5.0V or 3.0V)

GND = GND pin which must be connected to ground

TMS,TDI,TDO,TDI = JTAG pins which must reserved for the JTAG interface

NC = Unused I/O pins which must be unconnected on the board

Universal-Interconnect-Multiplexer assignments
------------------------------------------------
FanIn assignment for block A [6]
{
ENS,ENR,
RUZ,RUS,RUR,
SLA,
}
Multiplexer assignment for block A
RUZ (MC3 P)   : MUX 0 Ref (B22p)
RUS (MC2 P)   : MUX 4 Ref (B23p)
ENS (MC5 P)   : MUX 6 Ref (B24p)
SLA (MC6 P)   : MUX 14 Ref (B19p)
ENR (MC4 P)   : MUX 31 Ref (B27p)
RUR (MC1 P)   : MUX 34 Ref (B26p)

FanIn assignment for block B [6]
{
ENS,ENR,
RUZ,RUS,RUR,
SLB,
}
Multiplexer assignment for block B
RUZ (MC3 P)   : MUX 0 Ref (B22p)
RUS (MC2 P)   : MUX 4 Ref (B23p)
ENS (MC5 P)   : MUX 6 Ref (B24p)
SLB (MC6 P)   : MUX 8 Ref (B21p)
ENR (MC4 P)   : MUX 31 Ref (B27p)
RUR (MC1 P)   : MUX 34 Ref (B26p)

Creating JEDEC file C:\WINCUPL\U180.jed ...

TQFP44 programmed logic:
-----------------------------------
NR1.D = (ENR & !SLA);

LADSN.D = ((RUR & RUS)
# (RUZ & RUS)
# (RUR & RUZ));

NR2.D = (ENR & !SLB);

NS1.D = (ENS & !SLA);

NS2.D = (ENS & !SLB);

PR2.D = (ENR & SLB);

PR1.D = (ENR & SLA);

PS1.D = (ENS & SLA);

PS2.D = (ENS & SLB);

RUSN1.D = (RUR & !RUS & !RUZ);

RUSN3.D = (!RUR & RUS & !RUZ);

RUSN2.D = (!RUR & !RUS & RUZ);

ZERO.D = (!ENR & !ENS & !RUR & !RUS & !RUZ);

NR1.C = !CLK;

LADSN.C = !CLK;

NR2.C = !CLK;

NS1.C = !CLK;

NS2.C = !CLK;

PR2.C = !CLK;

PR1.C = !CLK;

PS1.C = !CLK;

PS2.C = !CLK;

RUSN1.C = !CLK;

RUSN3.C = !CLK;

RUSN2.C = !CLK;

ZERO.C = !CLK;


TQFP44 Pin/Node Placement:
------------------------------------
Pin 1  = TDI; /* MC 4 */
Pin 7  = TMS; /* MC 9 */
Pin 10 = PR1; /* MC 11 */
Pin 11 = PS1; /* MC 12 */
Pin 12 = NS1; /* MC 13 */
Pin 13 = NR1; /* MC 14 */
Pin 14 = RUSN2; /* MC 15 */
Pin 15 = LADSN; /* MC 16 */
Pin 18 = PR2; /* MC 32 */
Pin 19 = PS2; /* MC 31 */
Pin 20 = ZERO; /* MC 30 */
Pin 21 = NS2; /* MC 29 */
Pin 22 = NR2; /* MC 28 */
Pin 23 = ENR; /* MC 27 */
Pin 25 = RUR; /* MC 26 */
Pin 26 = TCK; /* MC 25 */
Pin 27 = ENS; /* MC 24 */
Pin 28 = RUS; /* MC 23 */
Pin 30 = RUZ; /* MC 22 */
Pin 31 = SLB; /* MC 21 */
Pin 32 = TDO; /* MC 20 */
Pin 33 = SLA; /* MC 19 */
Pin 34 = RUSN3; /* MC 18 */
Pin 35 = RUSN1; /* MC 17 */
Pin 37 = CLK;

** Resource Usage **


DCERP Field = Summary of Allocations.
|||||
|||||_Preset [p,-]       ==  p = PT preset, - No Preset.
||||
||||__Reset [g,r,-]      ==  g= Global AR, r = PT reset, - No reset.
|||
|||___Clock Enable [e,-] ==  e = Product Term, - always enabled, - none.
||
||____Clock [c,g,-],     ==  c = Product term, g = Global term, - No Clock.
|
|_____Type [C,D,L,T],    ==  Register type C= combin, D=dff, L=latch, T=tff.

For input only = INPUT.

MCell Pin# Oe   PinDrive  DCERP  FBDrive  DCERP  Foldback  CascadeOut     TotPT output_slew
MC1   42        --               --              --        --             0     slow
MC2   43        --               --              --        --             0     slow
MC3   44        --               --              --        --             0     slow
MC4   1    --   TDI       INPUT  --              --        --             0     slow
MC5   2         --               --              --        --             0     slow
MC6   3         --               --              --        --             0     slow
MC7   5         --               --              --        --             0     slow
MC8   6         --               --              --        --             0     slow
MC9   7    --   TMS       INPUT  --              --        --             0     slow
MC10  8         --               --              --        --             0     slow
MC11  10   on   PR1       Dg---  --              --        --             1     slow
MC12  11   on   PS1       Dg---  --              --        --             1     slow
MC13  12   on   NS1       Dg---  --              --        --             1     slow
MC14  13   on   NR1       Dg---  --              --        --             1     slow
MC15  14   on   RUSN2     Dg---  --              --        --             1     slow
MC16  15   on   LADSN     Dg---  --              --        --             3     slow
MC17  35   on   RUSN1     Dg---  --              --        --             1     slow
MC18  34   on   RUSN3     Dg---  --              --        --             1     slow
MC19  33   --   SLA       INPUT  --              --        --             0     slow
MC20  32   --   TDO       INPUT  --              --        --             0     slow
MC21  31   --   SLB       INPUT  --              --        --             0     slow
MC22  30   --   RUZ       INPUT  --              --        --             0     slow
MC23  28   --   RUS       INPUT  --              --        --             0     slow
MC24  27   --   ENS       INPUT  --              --        --             0     slow
MC25  26   --   TCK       INPUT  --              --        --             0     slow
MC26  25   --   RUR       INPUT  --              --        --             0     slow
MC27  23   --   ENR       INPUT  --              --        --             0     slow
MC28  22   on   NR2       Dg---  --              --        --             1     slow
MC29  21   on   NS2       Dg---  --              --        --             1     slow
MC30  20   on   ZERO      Dg---  --              --        --             1     slow
MC31  19   on   PS2       Dg---  --              --        --             1     slow
MC32  18   on   PR2       Dg---  --              --        --             1     slow
MC0   40        --               --              --        --             0     slow
MC0   39        --               --              --        --             0     slow
MC0   38        --               --              --        --             0     slow
MC0   37        CLK       INPUT  --              --        --             0     slow

Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades
A: LC1 - LC16 6/16(37%) 8/16(50%) 0/16(0%) 8/80(10%) (6) 0
B: LC17 - LC32 7/16(43%) 16/16(100%) 0/16(0%) 7/80(8%) (6) 0

Total dedicated input used: 1/4 (25%)
Total I/O pins used 24/32 (75%)
Total Logic cells used 13/32 (40%)
Total Flip-Flop used 13/32 (40%)
Total Foldback logic used 0/32 (0%)
Total Nodes+FB/MCells 13/32 (40%)
Total cascade used 0
Total input pins 12
Total output pins 13
Total Pts 15
Creating pla file C:\WINCUPL\U180.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...

----------------  End fitter, Design FITS
$Device TQFP44 fits
FIT1502 completed in 0.00 seconds


[Zondar]

Thanks MiDi for looking into that.

I haven't tried the CPLD's fast mode, but I had measured the rise/fall times to be 3.3 and 2.2 ns using the default settings. That was with no switches installed, but with a ~12 pF scope probe on it, so I wouldn't expect much change. That's already reasonably fast, and so I doubt that speed would be an issue. On the other hand, if wanghar had changed that setting (I haven't heard that he did), I'll try it now.

Earlier, I had put a fixed resistor in parallel with the 24k one, based on the results of my trimmer box. That worked just as well as the box yesterday, but today it wouldn't cooperate. I put my 1.1 MOhm trimmer box back on and found that I could get the board to run again (for a few minutes at a time). However, I had to drive the 5V reference to 5.15V (about the same as yesterday), which I'd judge to be an anomalous state that is not a proper solution to the 114 problem.

As MiDi points out, the default for the CPLD is with pin-keeper ON. Therefore, leaving unused pins floating vs. grounded should not be an issue.

I did try closing the inner cover over A3, etc. (not the outer case covers), but that didn't change anything that I could notice.

Another observation is that allowing the machine to warm up, even with the covers off, helped.

[iMo]

It is not only about how fast are the edges but about the proper sequence/timing of the edges as well. It may happen there is an unwanted propagation delay somewhere (or a missing synchronizer, metastability, timing glitches, etc.) which messes with the timing in a subtle way (from time to time, or at a specific sequence only)..

Kleinstein indicated couple of times here the values and TC of the resistors you have there may not demonstrate those errors per se. So what else? Those excessive capacitancies? Issues with the cpld?

PS: especially in case your cpld logic design is asynchronous (ie. all the events inside the cpld do not happen at rising edge of a single global clock) the doublechecking of the proper timings of all signals there is important, imho..
Btw, in case of such an async design every source compilation may give you different timings..

[Zondar]

All CPLD outputs are synchronized (to first order) by edge-triggered latches at each output pin every 50 ns. The total propagation delay between clock and output is about 7.5 ns. Given how much smaller 7.5ns is compared to 50ns, there should not be any issues with metastability, "missing" synchronization, etc. I'd guess that the genuine U180 might be a little faster, but I think CPLD issues are not a major suspect here, especially as wanghar and my boards use the same CPLD with the same code. A caveat is that I have not yet observed the timing of A3's FPGA outputs vs. the clock.

I don't think we know what the switch-related capacitance of the genuine U180 is. There is only a guess that it's lower since it's more integrated (I'd buy that). However, there's a fair amount of stray capacitance on A3, as well as an explicit 200 pF capacitor on the node Kleinstein was pointing to. Also not very likely to be the problem.

Kleinstein brought up the socket. However, its resistance is tiny compared with the switch resistance, never mind that of the 80k, etc., resistors. My board has gold-plated pins in a high-quality gold-plated socket, too. I don't see much there to be concerned about.

One suspicion is that small differences in resistances somewhere, either on U180 and on A3 or both, are to blame.  MiDi measured or listed the switch resistances, which I'll repeat here:

"rusn1 ~14Ω
rusn2 ~3.5Ω
rusn3 ~9Ω
ladsn ~12Ω
zero ~30Ω
all measured to sum"

These should net well under a tenth of a percent difference vs. our boards. (I do note that none of these appear to be quite in the 1x, 2x, 4x ratios that U180 was supposed to provide, but that's a different issue.)

MiDi: do you have measured data on U180's resistor values?

Wanghar, you stated that your "precision related" resistors are all 0.1% and 10ppm. If any differ, can you please list the values and specs for all of them?

This is what I have loaded in both boards now:

50k: 0.01%, 5 ppm/C.
80k: 0.1%, 10 ppm/C.
20k: 0.01%, 2 ppm/C.
10k: 0.01%, 2 ppm/C.
24k: 0.05%, 10 ppm/C.
37.4k: 0.1%, 10 ppm/C.
16.7k: 0.1%, 25 ppm/C.
4.12k: 0.1%, 10 ppm/C.
5.97k: 0.05%, 5 ppm/C.

I could swap in a 0.01%, 2ppm 50k, and 0.01% 6k and 4.12's (the last should have been 4.14, actually) now, if I wanted.

[MiDi]

MiDi: do you have measured data on U180's resistor values?

In the attachments are all resistor values: https://www.eevblog.com/forum/metrology/so-i-have-a-mint-condition-agilent-3458a/msg6043245/#msg6043245

[Zondar]

Thanks MiDi.

I've been attempting to measure the resistances within my own genuine U180. I'm seeing a phenomena I've experienced in the past but have no good explanation for: If I measure a single isolated resistor, the value settles immediately and remains quite stable down to the expected noise level. But if I measure a resistor network (one not connected to any supply or active circuit), the value creeps with a very long time constant (tens of minutes, even). A simple example is the 6k/4.14k resistor network. The amount of this "creep" is significant relative to the accuracy of the meter, and it makes it impossible to feel confident that the value is reading correctly. What is going on?

The values are not terrifically precise, though. For example, the 50k ~= 49.724k, 6k ~= 5.987k, 4.14k ~= 4.131k.

Note that my machine's serial number is within the batch noted to potentially suffer from drift (and it certainly did).

[wanghar]

On board #2, cut the pin 53 (GND2) of the PGA-65 socket and flying wire to GND. The power-on self-test passed without issues an then threw Error 114. After re-adjusting the 24K parallel resistor the Error 114 was resolved, and it is now running continuously. How is this related to the -0.6V Vss？

[Kleinstein]

When not powered the switch part can still have some residual resistance. The voltage from the resistance measurement can be enough to parasitically power the switch part too and this can be a rather slow rise in the voltage via diode and capacitance.

The values for the 50 K , 6 K and 4.14 K should not effect the error they would all only effect the ADC gain, like a slightly different ref. voltage. So there is little need to exchange those. There resistors have rather low need for accurate values, only want a low TC to get a final low gain TC. For just getting the ADC running these 3 resistor are not critical. So there is little need to exchange these.

If at all one could consider changing the 37.4 K to 37.5 K (as 2x 75 K stacked) to get closer to nominal.  Anyway the lower resistance there should still be just inside the tolerance and more have an effect like a higher 5 V level. So I don't think it would explain the issues.

The 80 K resistors provide some 150 µA ref current and 0.1 % error there would only be 0.15 µA. This should not be enough to disturb the 1.1x µA current for the last slope very much. It still looks like the part to have the strongest effect from tolerances. In theory one could reprogram the CPLD to swap the 80 K resistors and thus use the other pair during run-down.

Even with the 200 pF already there, the switch capacitance could still effect ringing. After all it is 200 pF and not the more common 220 pF and this may indicate a rather fine tuned capacitance. Much of the switch capacitance is also on the other side of the ferrites. I would still not expect a ringing problem for the run-down, as this is with small steps. More ringing could cause more an INL issue from short pulses in the run-up.
How large the capacitance of the switches in the original U180 is, is still open. The higher R_on and only NMOS switches point towards a low capacitance, while modern chips use finer structures (shorter channel) and this way lower capacitance than older chips. I still think it would be more on the lower capacitance side, as a high capacitance would become a noise issue.

If looking at the integrator output is not working (too much noise), one could check the signals at the HC14 to see how long the times for the slopes can get. It would still need looking at many captures with a small voltage at the DMM input: like 0-100 mV in the 10 V range, non Az mode with 200 µs integration to get a short run-up for a practical scale and low noise.

Using GND instead of the -0.6 V Vss would effect the run-up part, e.g. via the switch speed and maybe get less ripple there. If this fixes the inital startup error, this would be an easy fix. There is a chance that the ADG788 switches need more supply current than the original U180 switch part and this could cause problems. The idea with a -0.6 V voltage to drive the gates would be less leakage.

[wanghar]

Borrowed a 3458A, let it warm up for about 4 hours, and used it as a reference to perform zero and 10V calibration. Did a quick comparison test. Can you tell from the video which one is with the original U180 and which is with the hand-soldered NU180?

on #2 board.  Both @30plc, AZmode
More data will be coming!

[Zondar]

Wanghar: Are you saying that changing GND2 to GND resulted in a major improvement? I thought your board was working well without that change. Can you say more? Thanks.

[Kleinstein]

The test with a fixed 10 V is not that useful for the ADC. This test to a large part tests the reference in the meter and the external ref. also.
One test more ADC specific is to look at the noise with a shorted input. This could be at 1 PLC or 10 PLC. No need to use longer integration as this is usually just averaging.
In stead of a video a graph with voltage readings and maybe temperature vs time would be more useful.
For the initial version the TC and gain drift may be a bit higher - that is the point to improve with really good resistors.

The other point is than the DNL, to check if the fine slopes as they are supposed too.

[Zondar]

Wanghar: I tried it, and unfortunately I don't believe that change helped at all. In fact, I think the 114 problem is distinctly worse now. Even with adjusting the 24k resistor to a crazy degree, I can't get the board to operate for more than a single conversion or two, and usually it just fails immediately.

I guess I have to figure out how to get a pin back in there. It won't be easy. 

Can you please list all resistors with their values and specs?

Kleinstein: The switches are designed to operate with a negative Vss while the logic levels start at 0V. There is no issue with that, and I did test it to make sure.

I'm still confused about the resistor network reading problem. I can't get a proper reading of seemingly any resistor if it's part of a network with other resistors. That's true even though there are no other components involved. So for example, reading the 50k resistor on my board is trivially easy (it's a single isolated resistor), but the 50k resistor on the original U180 "creeps" because it's actually a network of 4 resistors (with nothing else attached). I left my meter on it overnight, and the resistance measurement continued to creep up, to the point that it added 80 Ohms to yesterday's measurement. Similarly, I can't properly read the 6k/4.14k resistors on my boards. What is going on?

I'm not sure what to try now. Maybe I'll cobble together a third board.

[wanghar]

A quick INL test is done, and the result looks really good. Here's the setup: one 3458A with a genuine U180, and another with a "NU180". Using the real 3458A as a reference to calibrate the unit under test. Both meters were hooked up via GPIB to sample data simultaneously from the same voltage source. The data is ported into spreadsheet for analysis.

[iMo]

..but the 50k resistor on the original U180 "creeps" because it's actually a network of 4 resistors (with nothing else attached). I left my meter on it overnight, and the resistance measurement continued to creep up, to the point that it added 80 Ohms to yesterday's measurement. Similarly, I can't properly read the 6k/4.14k resistors on my boards. What is going on?

A scenario - provided your ohmmeter is working fine the U180 50k creeping might be caused by moisture/residuals - while measuring them they get a little bit warm and the moisture evaporates slowly thus changing the conductivity. With your 6k/4.14k the flux residuals and moisture on your pcb may do the same..

[wanghar]

Zondar, I don't think removing the -0.6V Vss actually improves the board's performance – I only did it to pass the power-on self-test. While I haven't run systematic tests yet, based on limited verification, my current board shows decent characteristics in both noise and INL. It might be too early to draw firm conclusions, but it's definitely worth further validation.

As for solving the Error 114, I tried adjusting the 4.7K resistor (to fine-tune the ±12V reference) without success. Tweaking the 37.5K and 16.7K resistors didn’t yield good results either. However, adjusting the 24K resistor did work. So far, I’ve only tuned two boards – I probably need to test one or two more to further verify the repeatability of this trim point.

By the way, voltage modulation might help with noise and INL – some of my earlier tests support this idea.