Ultra Precision Reference LTZ1000

[MisterDiodes]

Digilant makes some good points, but there other factors too.  The drift story actually begins much earlier in the manufacturing process.

One of the huge mechanisms affecting initial drift rates happens when the die is separated from the wafer - the more energy and stress that's put into dicing the wafer into individual chips - this can cause larger fluctuations in the inertial crystal lattice strain, especially near the chip edges.

Once the wafer is diced, each chip now has to distribute the newly created edge strain around each newly formed faces on four sides - and whether this happens from the wafer saw, diamond scribe or laser scribe process will affect the crystal lattice - and thus electron migration properties.  The crystal lattice can not be the same near an edge as it is in the main body of the die.  So just the fact that the chip is separated from the original wafer starts the stress drift process from the exact moment it is born.

If the die has rough, dusty edges that means it has a lot of stress raisers that will affect all electrical properties as it heats.  Some of this we can't control, and is just the physics of the substrate itself.  Some die will work better because they were handled better or the original substrate batch was easier purified.  At every step the variations are minimized, but in the end each substrate batch is slightly different, and therefore so is each die.  It is just the nature of the beast.

For instance:  You can measure a diffused resistor in a circuit while the die is in company of all its neighbors on a wafer, while its all one piece.  Now dice the wafer into chips by whatever process, and then temperature cycle to help re-distrubute stress.  Those resistors (especially on die that were originally near the wafer edges) will now have different properties - because the substrate they sit on has now been altered.  The die near the edges of the wafer will change differently than the die near the center, and so on.  Also, how these chips re-distribute the stress created by making lots of new faces is also time variant - so some die will relax faster than others.  Wherever there is a change of crystal lattice, you have strain - and strain is everything.  All properties of the lattice - both electrical and mechanical - are changing in areas where the substrate lattice is stressed.

On some substrate materials, like those used for laser diodes (say InPh. GaAS, etc), we can cleave the edge onto a near perfect lattice plane, and that in itself produces a crystal edge with fairly low stress and strain - and is fairly stable as it heats and goes through billions of high-range temperature cycles.  But these substrates do not lend themselves to making particularly good buried zeners.

Then there is the die attach and wire bonding process:  Each of these can put an additional strain on the substrate crystal lattice - some of which can be controlled, and some that can't. 

If you try to make an absolute reference and use a laser to trim resistors on a chip - you also just changed the lattice strain again from the laser heat.  And guess what:  Now the device will behave and drift just a bit differently than every other chip in the batch.  That's one of the reasons absolute refs drift much, much faster than buried zeners. 

Realize that when a wafer is separated and during the wire bonding process, there are regions of the substrate lattice that are liquified for a very brief  instant, and the freeze again into a crystal or can even change into an amorphic region in some cases.  This event can form a new crystal plane depending on the cooling rate; and if its not in perfect alignment with the main substrate, you have a new area of stress.  You can't get away from it.

All of the above effects can be measure acoustically and with Atomic Force microscopes.  You can measure the crystal planes and internal stress pretty accurately, but you can't really cure lattice plane troubles once its in the chip.  You have to minimize these effects during manufacture - and that's the hard part.

What you have to realize when you're building a good Voltage Reference:  You aren't building a voltage reference at all.  You want to build a very in-sensitive thermometer out of something that at atomic scales is really as unstable as "Jell-o" when you look at it close enough.  Getting a steady, non-drifting voltage out of the device is just a by-product of how much of a "bad thermometer" it is.  In other words - everything in the die is related to how electrons move through the lattice, which is all related to heat and stress.


 

[CaptnYellowShirt]

... how these chips re-distribute the stress created by making lots of new faces is also time variant - so some die will relax faster than others.  Wherever there is a change of crystal lattice, you have strain - and strain is everything.  All properties of the lattice - both electrical and mechanical - are changing in areas where the substrate lattice is stressed.

This is the conclusion I'm starting to come to though my academic reading.

I'm surprised that there isn't more written on the topic. I have found tons of material on the reliability of semiconductor technology (including zeners) with respect to conditions that lead to complete failure. However,  I've found very little on the subject of drift. The literature shows me: 1) that it does happens, 2) when it happens, 3) how to predict it happening, and 4) how to correct for it. But I'd like to know more about the underlying causes of it.

I'm familiar with the relationship between band structure and strain. Are there any books or papers that deal with the 'art' of semiconductor production -- specifically dealing with stress, creep, and band structure interaction?

[rf-design]

If all aging is because of stress change, either from die internal stress or from die external stress from the adhesive die attach what would be the impact on the final reference voltage?

To my knowledge the stress changes the bandgap voltage. That would impact the final temperature point because the regulator is based on Vbe. But up to now I do not know a direct effect of stress on the zener voltage.

Is there a significant effect on the buried zener?

[MisterDiodes]

Capn': At the company I work for we build some of the equipment used to dice wafers into individual chips, and especially laser diodes, and we solve problems like these for manufacturers.  What we tend to see are the guys on the production line that notice these drift effects on analog (and sometimes digital) circuits, but sometimes the design engineers laying out the circuit masks are half a world away and don't really get to see the hands-on interaction of what's -really- happening at chip level production.  And the Fab line won't talk to Engineering, &  vice versa. And the bean counters just want good sales, not necessarily good parts, so good engineering investigations (that take TIME) don't get rewarded very well. Not all the time but we see it a lot - just how big corporations tend to work.  Sometimes people want to just come to work, push some buttons, get paid, and go home. 

Granted, when you're working at the wafer / chip level you can't even see what you're working on without a microscope - but you -can- study these stress & drift effects.  Its like working with PCB's except much, much smaller.  With a wafer prober, an acoustic microscope (these generate say 1Mhz mechanical waves that we inject sideways into the wafer to watch for reflections - i.e. stress - in the whole wafer) and generally an Atomic Force microscope, where we scan the wafer surface and look for out-of-place crystal planes buried inside the wafer - again this translates to strain & stress in the crystal.  Almost always this will turn up later as a drifting analog circuit later on.

I been at a facility, training people on a new piece of equipment, and they will put on a wafer to dice up into chips - mind you nobody knows what it is, because Engineering didn't tell them.  But I can look at the chip and tell them "Uhh these resistors / transistors / diodes that are over here right on the edge of the die are probably going to be trouble. Just sayin'".... and sure enough in a few weeks after they get 98% rejection during test the production circuit mask gets changed.  That's happened more than once - but it shouldn't happen very often.

What's frightening is the new designers just starting out that lay out masks - and blindly trust what the CAD software produced.  You have to really look at the whole circuit / wafer / die as a whole system, then build some, then test & tweak - no CAD software is a substitute for hand's on experience.  Sorry, Mentor Graphics. 

And strangely enough, you can't Google the answer to some of these questions - you have to go in the lab and study, test, and re-design sometimes until it works.  And the bean-counters really, really hate that... <Laughing!>

[quantumvolt]

@MisterDiodes

Allow me to say that I really like your posts. They have a certain flavour of theoretical knowledge mixed with hands on experience.

There is a picture of the internals of LTZ1000 in this thread (and on the web). Could you and/or others who feel competent, give us an introduction on how to 'read' it?

[MisterDiodes]

My favorite sign on my office door - someone gave it to me and its floating around on the web - and I think this is a good description if the this whole thread - and in particular ultra precision voltage refs:

"Where Theory Ends and Reality Begins"

About looking at Die Photos - very,very short story - :
Usually the manufacturers get really upset if you publish a highly detailed images and description of their complete mask pattern - and Linear Technology, Intersil, Analog Devices, etc. are our friends, so its probably best to not go into high detail here. That is their IP.

For Fun: Generally when you're looking at an analog die in the microscope (much easier with your eyes, not a video or photo), anything gold or pink-ish or borwn-ish gold is a conductor.  It depends on what metal was deposited on the die for conductors, and there are myriad combinations.  Sometimes you see where conductors cross and you can make out the insulator (or resistor) between the conductors.  On RF devices it is not uncommon to see square coil structures or waveguides, and sometimes these will have a delicate Air Wire crossover - where you literally have conductor lift up and over another conductor like a freeway overpass - and there is nothing but air in between - a matter of a few microns or less sometimes.  At high frequencies that crossover is also acting as a capacitor or virtual inductor too.  Terminology varies by manufacturer.  But typically you won't see these on Vrefs.

Remember also - when you're looking at a die, you're only looking at the top layer.  If you're doing a real investigation, you can etch away the various deposition materials, and go down into the die layer by layer.  But you can usually get a general idea by looking at the top.

Resistors can be darker brown / black, or will appear yellow or dull grey (for deposited foil).   Its good to use vertical illumination on the microscope so you can really see the contrast (generally not a ring light here) and detail, and you want adjustable zoom.   Follow the path from the wire bond pad, have the schematic in hand and start tracing - and don't forget the substrate is part of the action also - or not.  Depending on how the device is made the substrate can be a 100% insulator, or if its been doped it can be a diode junction to ground, or what they generally call "backside metalization", which would be metal (usually sputtered aluminum / gold but can vary) on the bottom of the device.  Its easier to tell when you're looking through a microscope directly because you can change the light / focus and get an idea of what areas are taller / shorter.  You can usually see larger fets and BJ transistors - some can be pretty hard to see without going to high magnification.  Out at the very edge of the die you can see what's called the "Scribe Street" or "Wafer Channel" and this is usually where you can see the surface of the substrate itself, before it had the circuits masked on more near the middle of the die.

If you have a stereo scope with a Nomarski filter / illuminator system, you can see flat surfaces in sharp detail and high contrast - for instance if you're looking at the edge of the die, you can tell how it was diced apart from the main wafer.   Its in the Channel where the device was separated from its neighbors, and how rough or chipped out that side face is tells you how well the dicing process went that day (think like your looking at a bullet's rifling pattern or the edge of a sawn wooden board)) - and the Nomarski will really bring that detail out.  If we see chips that had a lot of trauma on the edges - something was either wrong or the channel had some sort of grey nitride passivation applied, which is a real challenge to separate - because its almost as hard as diamond.

The heater resistors will probably a pattern of a zig-zag repeating pattern back and forth, and judging by the simplified schematic on LTZ1000a's these are probably diffused into the substrate itself, without an insulating layer -  that's why there is a "diode" junction circuit between them and down into the substrate proper.  That is just an educated guess though.

[CaptnYellowShirt]

For those of you who haven't seen the pictures...

We can thank our Russian and Chinese counterparts for posting them.

[MisterDiodes]

The structure in the center is the Zener, where it should be, surrounded by the heaters.  Of even more interest to drift studies: In the larger monochrome photo you can see the die edges.  They are fairly rough, and characteristic of what happens when silicon is sawn.  This isn't too bad, but realize at each of the those chipped out places is a spot where the die will be -very- highly stressed during heating / cooling.  Normally this isn't a huge issue for most circuits, but when we're shooting for sub ppm..."everything" makes a difference.  Again, the crystal lattice can not be the same at the edges as it is on the interior of the device, so the more edges there are, the more stress in that region of an edge (this wafer has ~millions of small edges on each side face).

Short Story: If we were to measure that die acoustically, say transmitting at some Mhz from the left edge to the right edge (without any circuit placed yet) - we would see an echo ping that would measure say maybe 3/4's the way across the device.  The sound wave going left to right would reflect off the edge stress discontinuity region in the crystal lattice, not the actual right edge - and then travel back to the left edge - and by timing the arrival of the reflected pulse we can tell how much of the die is actually acting as single crystal.  The speed of sound through the material changes at a discontinuity of the stress region, and we can use that to determine how good the substrate is after its diced into a chip.  It works just like if you were measure a cable with a Time Domain Reflectometer, or shining a laser at a piece of glass - you get a reflection wherever the wave front changes speed.   Simply:  When you measure the die size acoustically, and the closer your acoustic measurement correlates to the actual die size, the better edges you have, because that means there are no big large discontinuities inside the crystal.

The above is a simplification, but you get the basic idea.  There are more details, but I'm kind of distilling it down to the bare basics.

On some materials, like GaAs or InP, there are vertical crystal planes normal to the top surface, so we can cleave a -perfect- mirror edge with a diamond scribe process.  Silicon substrates like these will have a crystal plane running 45° to the top surface (which means a cleaved crystal plane  would leave an angled edge), and so these devices shown in the photo are typically sawn or laser scribed.  These processes leave vertical edges, but rough - because the crystal has no natural plane in that direction.  If you look at the side face you will see small short faces following the crystal plane, never a smooth surface.  And therefore it is will have much higher strain levels near the edges.  If you had an amorphic material like glass, you could achieve a smooth face if you polished it out, but not really with a single crystal if the edge is not lined up to an atomic plane.

So maybe on the die you're looking at, the middle 50% area of the die is probably low-stress, and the internal strain increases as you get closer to the edges - with highest stresses typically in the corners.  That's one of the reasons we try to avoid the corners as much as possible for critical circuits, or use those for non-critical or digital I/O.  These designers did very well - the chip is large compared to the circuit, and the business end of the device is in the middle - where stress changes are smallest. 

Still: If you were to measure the Zener at a known current while these die were in a whole 4" wafer (or whatever size they make these on - 2" thru 6" diameter are common) - and then measure the exact same device after dicing, the device characteristics will be -slightly- different.  Yes, even though the chip-outs and edges are relatively far from the zener.  We're talking ppm here.

It is my theory that this - and other lattice stresses that are induced during manufacturing -  is what contributes to initial drift, and then as time moves on the drift is more dominated by basic electron migration across junctions.  Which is a slow process, but will still happen faster at higher temperatures.  Electrons at higher energy will statistically have a better chance at crossing a PN junction.  Heat the die hot enough and the junctions will become useless.

I think one of the main reasons these buried Zeners work better than anything else is that they are -not- laser trimmed.  Laser trimming gets a desired output voltage, but with damage to the underlying substrate - and that damaged lattice certainly contributes to long term drift.  If that effect can be minimized, the better the device will be.  The Intersil Vref uses a floating gate to acheive a ref voltage, but that has a whole other set of problems.

I think in the end, to be practical there is only so much that can be done with external devices to correct for drift with buried Zener references - that's why when we built these with Wirewound or expensive Vishays for load resistors, the results we had 10 years later the results are not that much different - the Wirewounds stood up even better over time, and are one tenth the cost.  You can control drift up to a point working "outside" the package, and some of the drift is built into the device itself.

So that's why we use other approaches to build a stable calibrator box:  Don't use just one Vref, build a box with 4 or 10 or 25 or 250 refs inside, and average the best performers.  At the very least you get a calibrator standard where you know the whole box is drifting slowly one direction <Grin!> and you still have to calibrate against other sources over time.

[CaptnYellowShirt]

So that's why we use other approaches to build a stable calibrator box:  Don't use just one Vref, build a box with 4 or 10 or 25 or 250 refs inside, and average the best performers.  At the very least you get a calibrator standard where you know the whole box is drifting slowly one direction <Grin!> and you still have to calibrate against other sources over time.

I love this idea of averaging an array of references. I've been thinking about it a bit on and off recently.

Personally, I see a set of zeners wired in series. If we assume that the fluctuations any one of them experiences w.r.t. time is uncorrelated then the errors add as the root of the square of the sums of their voltages (better than a simple linear sum). Here I'm talking about  error sources like crystal defects and the associated current constriction in the chip but not things like room temperature or atmospheric pressure. The downside here is if one of the zeners goes belly-up, you loose the entire set.

MisterDiodes: do you have any thoughts on these crystal defects? Its something I've only read about. What cause them? Processing speed? Bad design? Just random things noone can control?

[MisterDiodes]

CapnYellow: Regarding averagers for Vrefs:
This is a good way to tell if you have a drift problem, and the commercial averager standards will typically have 4 or 5 Vrefs.  I say if you've spent all this time losing sleep thinking about one Vref, coming up with good thermal management, getting good wirewound resistors and parts, etc - why stop at building just one?  Anything worth doing is worth doing to excess!  The building part is the least time you've spent and the cheapest if your time is worth anything, so I suggest you make up a batch of 5 or 10 or 20 Vref boards or whatever.  Burn them in and pick the best performers.  Keep a few spares, & give away the rest of the batch to your buddies to check their DVM's.  That's what I do.  You will be very popular.  Or just keep the extras  burning in longer, like a year or two longer, and sometimes they become useable over time.

People have to get used to much longer time scales when working with good Vrefs - when I say "burn in" that means at least -several- weeks - but for a good Vref let it burn in until it stops drifting too much - say 6 weeks ~ 6 months or maybe a year.  So another reason you might as well make up a batch of these instead of just one.

Put the good ones in a box and average them out electrically or computationally - measure each Vref's circuit deviation from the average, and if one Vref is mis-behaving you will know right away.  The averaging can be done with a master output op-amp, or you can use a CPU or FPGA to do a computational average to set an output DAC or whatever is fun for you.  All of these have been done.  It works.  In the end the simpler methods really work the best, though.

The "perfect world" theory says you'll get a reduction of noise by the square root of N Vrefs - so using 4 Vrefs should get you a noise reduction of about 1/2.  Sorta.  In my experience, if you actually do this you'll find you need more like 5 Vrefs to get a solid, honest noise reduction of 50% from where you started out.  Use 17 or 18 Vrefs to reduce the noise by 4, etc.  This is one of those times where you have number theory meeting up with reality - and reality wins every time. 

If it were me, I like to put the Vrefs on their own module board so swap-outs are easy.  But that's me.

In terms of reliability - Like I said we really haven't had much in they way of failures because the circuit has such a low component count, and the currents are low in the Vref itself.

BUT when you work with chip-scale circuits, and do forensic analysis on failures - you will understand why you want to keep your important equipment powered on - in general.  On those die edges, wherever there is a small chunk missing along the edge (a chipout) - that is a potential stress raiser where a crack can form when the die is under maximum stress - and that's when it is heating or cooling at the maximum rate.  i.e. when you turn the power on or off.  If the built-up strain is great enough to start the crystal lattice bonds breaking, then there is enough energy to drive a crack straight across the die.  Sometimes you get lucky where a crack can start and then turn around and run back to the edge, and in this case all that happens if you have another piece of substrate dust floating around in the can.

The other failure mode is at the wire bond pads - They are pretty forgiving, but given enough thermal cycles these can be another weak link in the chain.

Of course there are myriad other things to go wrong - an ESD zap, power supply failure, etc.

The worst is when you zap a die with static that has enough energy to just START a crack in the substrate, but it doesn't drive it far enough in to affect the circuit "today", but it will fail in 20 minutes or 20 years.  That's what we call a "very expensive service call crack".

The rule of thumb for bathtub mortality rates on simple circuits:  If the device works for at least a few weeks/months of torture-test thermal cycling & burn-in, it'll probably be fine for the next 40 or 80 years.  The above failure modes are a very good reason to do a very thorough burn-in before you put your Voltage Ref averager system into dependable service:  You want to break it right away if possible - and get the whole system as stress-relieved as you can.

[CaptnYellowShirt]

Fascinating. Again, thanks for the great info.

If you flip back several pages ( https://www.eevblog.com/forum/projects/ultra-precision-reference-ltz1000/msg404500/#msg404500 ) you'll see DiligentMind's conversation with LT and Bob Dobkin.

In this, he says the LTZ packages are back filled with dry air before they're sealed up.  What do you think about that in terms of stability? Is that a common practice?

[rf-design]

I guess that the passivation is not up to the level of modern CMOS process which require inert gas filling. It is a tribut on having a monolithic buried zener with bipolar based temp control.

Some posts ago I had taken a look at the avaible foundry processes beween 0.5u BiCMOS and 0.13u SiGeBiCMOS and there is no deep n+ to deep p+ implant or buried layer diodes avaible which could make the buried zener. So it seems that this old 1-metal, diffused isolated bipolar process is the only way to go for buried zener with bipolar temp regulator.

Some foundries offering zener but I guess there are all extend to surface because they are lateral built. So they they suffering from less stability because of the surface trap effect.

[CaptnYellowShirt]

So it seems that this old 1-metal, diffused isolated bipolar process is the only way to go for buried zener with bipolar temp regulator.

Have you found any source for a simple buried zener -- no compensation circuity included on the IC?

[janaf]

Lots of interesting reading in the LTZ1000 thread :-)

This is one of my first posts here.

Now a comment and question on the LTZ1000 circuit.

I made a breadboard with the same schematics as in the datasheet. The R2 and R3 values in the datasheet are given as 70K and R4/R5 as 13K/1K. I have made some measurements by making small changes (0.1%) up and down, to temperature setting nominal 1:13, while changing the value of R3 in steps from 40K (edit , extended from 60K) up to 130K. The result; lines straight as a ruler for the output voltage, with a constant 75uV per 0.1% change in R4/R5. This is about 1ppm/100ppm change of output, pretty close to what is specified in the datasheet.

The output also changes by a very constant 765uV per 3K change in the value of R3, over the whole tested R3 range 40K  to 130K, i.e. 0.185ppm change in output voltage per 100ppm change of resistor value at 70K, as given in the datasheet. This is slightly better than the 0.2ppm / 100ppm given in the datasheet.

The interesting part is that it seems one could use just about any value for R3, at least between 60K and 130K. A value like 100K would seem very practical. High values would be preferred as the sensitivity to resistance errors will be lower, but one may run into stability problems if the resistor value is too high / currents get to low. I used the 2N3904 for the NPN.

Any thoughts on this? Anyone made similar measurements?

I also made some measurements at 1:12 (1K:12K) for R4/R5 but the stability is not as good as for the higher temperature setting of 1:13. This is especially true for R3 values above 80K or so.

[Andreas]

Any thoughts on this? Anyone made similar measurements?

Hello,

I have made tempco measurements over change of the 70K resistors.
In my design there are a 50K + a 20K in series.
So I wanted to save the 20K.

But with 50K instead of 70K the tempco of the reference slightly increases when I change the temperature setpoint from 50 to 60 degrees.

Btw.: 12K+1K for temperature setpoint is much too low for a LTZ1000A.
12.4-12.5K is the limit for the A-Device.

With best regards

Andreas

[janaf]

Turning the heater fully on-off, I got a tempco minimum (near zero) at 80K for R3 too. That matches what is indicated the datasheet and what is used for example in the 3458A DMM.

But making small temperature changes, I got the same tempco regardless of R3 value (range 40K to 130K).

So either

• I made some systematic mistake
• My circuit is different
• Measuring the R3-to-tempco with the on-off method gives other results than the small temperature step method, i.e. the correlation is non-linear.

If my measurements are right then there is no minimum for the R3=>tempco, but still just below the 0.2ppmV/100ppmR in the datasheet. The good news would be that "any" resistor value could be used for R3 and most likely for R4 too.

That's why I ask if someone else made measurements with small temperature steps, not the on-off method, and what the result was?

[Andreas]

Measuring the R3-to-tempco with the on-off method gives other results than the small temperature step method, i.e. the correlation is non-linear.

Hello,

I think we have to be more specific.
- Which device LTZ1000 / LTZ1000A ?
  My results are with 2 LTZ1000A references.
  With nominal setpoint 12K5 + 1K = 50.5 degrees C

- Kelvin sensing of the output voltage?
  my output voltage is directly

- Switchmode power supply?
  my setup is fully supplied from batteries all on a metal ground plane.
  switchmode noise gives a large influence on the temperature setpoint pin

On #1 I get 20.3mV output voltage change between heated / unheated. (22 to 50 degrees?)
With additional 22K resistor in parallel with the 1K (Setpoint = 61.25 degrees)
I get 3.7mV change or 48ppm/K

Changeing R2 from 70K -> 50K gives 4mV output voltage change for 50/61 deg C = 52 ppm/K.

On #2 I did only the test with 70K: with around 54ppm/K change on output voltage for a 10K step.

Since the tempco of the zener is around 50ppm/K I cannot imagine that you get a zero tempco with just changeing R3.

With best regards

Andreas

[Andreas]

Unfortunately the video is in French ... : 

Hello,

OMG:
that was the only protection that they could not copy the reference perfectly.
Now with the 2 hints they can. 

With best regards

Andreas

[TiN]

Buy from Linear and you will not have a problem

[Galaxyrise]

I have been trying to characterize my ltz1000.  I've got Q2 set up similarly to how Q1 is in the datasheet so I can measure it's Vbe, Q1 Vbe, Vz, and I have ammeters on pin 3, pin 5, and pin 8.  All three currents have been trimmed to 100uA. After making a bunch of measurements, I started to move towards a heated configuration.  However, it seems like applying any voltage at all to pins 1&2 is affecting all my other measurements, even if pin 1&2 are at the same voltage.  (I either have the heater at 1-10V or I leave it floating.) My guess is that I'm looking at some leakage current through those "substrate devices, do not forward bias", but it's causing millivolts of difference!  Is something wrong with my test setup, or is there something that mitigates this effect in practice?

[janaf]

Some characterizing I have done on the LTZ1000AHC

- Two ICs, two different boards, nominally:
- R1: 120R
- R2 & R3 68K
- R4 / R5 12.5K and 1K

Measured ranges:
- R1 120R, varied by +1%
- R2 & R3: 40K to 130K in steps of 3K and steps of 9K
- R4/R5: 12, 12.5 and 13, varied by +1%

Results

From a couple of hours of measuring, in total about 300 different data points

Output change versus resistor change i.e. ppmVolt/ppmOhm

• R1: -0.0014
  
• R2: +0.004
• R3: +0.0007
• R4/R5 ratio: +0.012

Some comments

- The sensitivity to R1 variation was surprisingly low, 92uV / 1R1, averaged over 25 step changes, all within 89-95uV / 1R1)

- Also the sensitivity to R3 was lower than indicated in the datasheet

- The R4/R5 sensitivity does not change at all with R3, but decreases slightly with increasing R2 (0.0125 to 0.0093 over R2 values from 40K to 130K)

- Output sensitivity versus R4/R5 ratio decreases, but marginally, over increased R4/R5 (0.0129 at 12.4, 0.0118 at 13.2)

- Stability for low R4/R5 at low values: stable at 12.4 at room temperature, not stable at 12.0, unless cooled to 18C. Stability increases with lower values of R2 and R3.

- Output versus load current: no measurable change (<1uV) to output with current sourced / drained between +5mA and -9mA. The output is very DC stable. (sensitivity to ripple voltage on the supply was not measured). When changing load, the voltage changed by up to 10uV at 0-5mA load

- Output change versus supply voltage: no measurable change to output (<1uV). This is as expected as the power supply is only to the opamps and the heater transistor. The circuit is very tolerant to input voltage level.

- Output change versus low supply voltage, near dropout: unmeasurable, <1uV, down to dropout at
7.5V supply. This is a characteristic of the opamp only.

- The LTZ1000A output voltage was measured directly on the IC pins
- The power came from a linear bench power supply and there was a AS2954 LDO regulator on the LTZ1000AHC board, set to 11V
- The measurements where made with a NI 4021, 7.5 digit DMM (LTZ1000-based)
- The LTZ1000AHC was tested on a PCB made specifically for testing, with breakout jumpers for all components
- The board was populated with thin film 25ppm resistors. The resistors that where varied, where wired from a separate breadboard, with 1% metal film 100ppm resistors.

If of interest I can post photos, data and diagrams...

PS: ignore the results in my previous posts, they where the result of regulation collapsing, using R4/R5 ratio of 12...

[Mickle T.]

Measurement results from lymex/BG2VO:

[TiN]

If of interest I can post photos, data and diagrams...

Please do

[janaf]

As I got some requests, I will post more, but give me a couple of days.

Thanks for posting the Lymex data. If we multiply my data by 100, for 100ppm resistor changes we get:

-	Datasheet	Lymex	Janaf
R1	1	0.14	-0.14
R2	0.3	0.4	-0.4
R3	0.2	0.03	-0.07
R4/R5	1.0	0.95	+1.2

A couple of conclusions:
- It seems the R1 and R3 values are not as critical as given in the datasheet. Or both Lymex and I are wrong.
- Put your money on R4/R5 and R2 while R1 and R3 are less critical.

In the end, the errors of resistors are uncertain , it is not meaningful to dive too deep into the decimals.
EDIT: changed signs in the table.

[janaf]

Galaxyrise, could you have damaged your LTZ1000? I's rated 0.1V max forward bias on the heater pins relative to pin 4 which would usually be at around 0.5V, ie pin 2 and 3 must always be higher than 0.5V