WCH $0.10 USD RISC-V MCU

[martinribelotta]

Now, Patrick just posted the 1-wire protocol of debug:
https://github.com/openwch/ch32v003/blob/main/RISC-V%20QingKeV2%20Microprocessor%20Debug%20Manual.pdf

I hope that this protocol be the same for ch32v307 and familly but addapting the transport to 2-wire interface (Man I need a weekend free to put a logic analyzer over CK and DIO lines on my ch32v307 board)

[gmb42]

A tiny $1.50 WCH dev board from Muse labs, the nanoCH32V003. See https://linuxgizmos.com/the-nanoch32v003-is-a-risc-v-dev-board-available-for-1-50/

[elecdonia]

I think it's fascinating that Chinese vendors seem to have started targeting American "hobbyists" - cheap development boards, free development environments, documentation in English (even if it's not very good documentation), chips for sale in retail quantities, etc...   I'm guessing it's due to the success of Espressif.  But it's certainly fun times!

I think of myself as more of a “frugal independent developer” than “hobbyist.”

I retired after a 20+ year full-time hardware/software design engineer position (at one company!). These days I still have plenty of projects but a much more limited budget compared to when my employer was willing to purchase (most) of the development supplies I requested.

I continue to support Arduino.cc, Raspberry Pi, adafruit, Sparkfun, and Teensy by frequently purchasing items directly from them. Without them we wouldn’t have either the hardware or the tools to make cost-effective embedded systems.

But I also find it irresistible to sample the enormous smorgasboard of Chinese clones, modules, boards, and tools. It costs almost nothing to try them out. Some items are junk. Others are quite well made and stable over time.

[HwAoRrDk]

Don't you just love it when there are inconsistencies between what a manufacturer's documentation says and what code in their HAL/SPL/etc actually does?

There are a couple of such inconsistencies I've noticed in the CH32V003 Reference Manual (as of latest available, v1.3).

First is to do with the RCC clock configuration register CFGR0. According to the Reference Manual, bits 10:8 are "reserved" and bits 15:11 are for ADCPRE (ADC clock source divider). But wait! The library headers give bits 10:8 as for PPRE1 (APB1 clock source divider), bits 13:11 as PPRE2 (APB2 clock source divider), and only bits 15:14 for ADCPRE.

Did they decide to throw out the ability to run APB1 and APB2 at speeds different than the main AHB clock in order to have a greater range of dividers for the ADC? It may be that the docs are correct, because the separate header file for the RCC peripheral defines its own set of values for the ADC prescaler field that match the docs, and they forgot to update the main header file (it seems to be a pattern that peripheral-specific header files define their own register constants, in duplication of the main header). Who to believe?

The second instance is with the I2C peripheral. The manual documents that bits 14:10 of the OAR1 register are "reserved", but yet the I2C_AcknowledgedAddress_7bit constant in the I2C header file has the value 0x4000, which has bit 14 set, and this constant is always written to the register by the I2C_Init function.

So what is this bit? It rang a bell in my memory, that I had seen something like this before. Lo and behold, the I2C peripheral of the STM8 has in its OARH register an ADDCONF bit 14 which is documented as "This bit must set by software (must always be written as '1')". Hmmmmm... Are WCH using the exact same I2C peripheral? Everything else seems to also be highly similar to that of the ST chip. Did they buy the same third-party implementation? Or did they clone it so well, they included the flaws too?

[josuah]

so, the ATTiny8 is done for, right? end of an era 

It will be when the power consumption will also match:

In standby, 25°, with the low speed oscillator running (for waking-up periodically and trigger an ADC readout for instance):

• CH32V003 - 10 uA - http://www.wch-ic.com/downloads/file/359.html
• ATtiny202 - 0.7 uA - https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/ATtiny202-204-402-404-406-DataSheet-DS40002318A.pdf

Not everything has lower than 1 uA battery consumption as requirement though.

[tim_]

VDDmin is also much lower for the ATtinies.

[MT]

CH32V203 manual.

In the Standby mode, the contents of 32KB of SRAM can be kept (depending on the planning and configuration before going to bed), and the contents of the backup registers are kept.

[SiliconWizard]

CH32V203 manual.

In the Standby mode, the contents of 32KB of SRAM can be kept (depending on the planning and configuration before going to bed),

Good night!

[Sacodepatatas]

Also CH32V203 Datasheet...

[1276-2449-1-ND]

... and configuration before going to bed), and the contents of ...

If you put your ear to it when shutting down you can hear it beep and buzz a little lullaby. 

[jnk0le]

FYI

With a bit cursed github workflow, I've got someones GPL-lettered openocd fork to build windows binaries.

https://github.com/jnk0le/openocd-wch/releases/tag/29042023

v003 confirmed to work and open eclipse debug session.
No idea about the rest as I don't own those and cfg scripting is cursed similarly to code quality (even compared to extracts from MRS).

EDIT: it turns out that it requires proprietary drivers to work (enumerate as WCH-LinkRV instead of WCH-Link). Zadig WinUSB doesn't work.

[jnk0le]

some notes after briefly debugging this thing:

- debugger cannot step over `ebreak` instructions (single step as well as "continue" option). However eclipse breakpoints do work. Probably something with openocd code.

- MIE csr register is non functional

- `mie` bit can be written (high) by csr instructions only when it's written together with `mpie` (must write 0x88 instead of 0x08).
Debugger can however write `mie` bit without touching `mpie`

- after a hard reset (remove power, short vcc to gnd), sometimes the `mpop` and `mppop` are set in `mstatus` register

- 0x744 in `ra` after hard reset (anyone else?)

[jnk0le]

Finally got the startup code a bit more optimized than the vendor one.
https://github.com/jnk0le/simple-crt/tree/master/ch32v003

while(1) is 208 bytes with static initializers (194 without), and blinky (volatile delay)  is 286 bytes.

ED: now it's 202, 188, and 280 bytes

[HwAoRrDk]

- MIE csr register is non functional

That's because it doesn't have an MIE register (nor MIP). The list of supported CSR registers can be found in the WCH QingKeV2 CPU manual.

Interrupt enable/disable/status are controlled by the proprietary PFIC peripheral using the PFIC_* registers (I say 'proprietary', but it's basically a clone of the STM32F103's NVIC).

[jnk0le]

Interrupt enable/disable/status are controlled by the proprietary PFIC peripheral using the PFIC_* registers (I say 'proprietary', but it's basically a clone of the STM32F103's NVIC).

Those are per interrupt ones somewhat redundant to the core `mie` in `mstatus`, and the ones inside peripherals.

[westfw]

a clone of the STM32F103's NVIC

Is the STM's NVIC anything different that the ARM Cortex-M3 NVIC?

[GromBeestje]

It is standard Cortex M