Experimental 48V->120VAC 60Hz inverter

[uer166]

Finally came round making my second power electronics project, and would like comments/feedback.. This is the continuation of https://www.eevblog.com/forum/projects/experimental-48v-gt200v-boost/ with some of the suggestions/ideas implemented.

The spec/concept is a simple 48V to 120VAC inverter for a portable backup power generator. The original idea was, 300W continuous output, with 600W peak for minutes, passive cooling only, and something like 95-97% efficiency. I dreamt up a topology one night, with the idea being, only a single non-isolated stage, and a pure sine output without high frequency
common-mode voltage output. It's simply two synchronous bidirectional boost converters, each generating 60V RMS that sits above the 48V rail at all times. The lithium pack would then be at some negative DC voltage relative to the output.

The goal was to make it as flexible as possible, with software/peripheral control, and be able to do things like dead-time vs. efficiency sweeps, and  try out all kinds of control strategies (BCM, peak current mode, average current mode, hysteretic, etc etc). Hardware-wise, it's two isolated half-bridge gate drivers with the high-side being bootstrapped. The inductor current is measured on the 48V (quiet) side with an INA240+shunt and works great. There is a latch to disable the gate drivers in case of overcurrent or a if both high and low sides are commanded on. This proved to be invaluable during bring-up, I would have blown-up 100 FETs trying to make the control scheme work! But so far not a single one has been electrically destroyed. All is controlled by a STM32G4 with a HRTIM peripheral and all the on-board goodies (COMP, DAC, OPAMP, ADC).

Currently I have variable frequency current control implemented, a simple hysteretic mode, and can either do BCM or CCM, simply by choosing the correct DAC thresholds for switching. It works nicely as a general purpose boost converter for any voltage up to 230V or so, 4-quadrant. Now onto the challenges/ideas.

Bootstrapped gate driver issues:
The bootstrapping of high-side has been one of the bigger headaches so far.
During the very first switch-on of low-side, the bootstrap needs to charge the cap. The problem is, I had a 10-ohm resistor in the path and it wouldn't let the cap charge enough to get the high side out of UVLO, and would lock-up the hysteretic control. Solution: make it 0-ohms, which then caused a bunch of oscillations in the 15 and 3.3V rail, wreaking havoc on the INA240 output. That was solved with lots of bulk capacitance on those rails. Another big issue now is, how to guarantee a minimal duty cycle that doesn't lock up? In a PWM modulator, it's trivial, but in peak/hysteretic hardware control, it seems impossible without some bolt-ons. If the high-side ever gets stuck in UVLO, the hysteretic control stops..

Reverse recovery losses:
At 300W 120V RMS output, the peak output voltage of each boost converter is 220V or so, a 4.5x ratio. The output current would be 3.5A, so, 770W (a big part is reactive power only)! The reverse recovery in CCM is vicious and causes all kinds of headaches, if anything, just the noise that seems to swamp the overcurrent protection and trips it constantly. The solution in original design were saturable core reactors in the source of each FET. They work amazingly well, but unfortunately melt themselves due to core losses within. I tried 4x in parallel and that does work, but does not improve efficiency unfortunately. After switching to SiC FETs this is still a problem. The only solution I found was BCM control for soft switching which fixes this completely, but introduces another issue..

Inductor core losses:
I've made a spreadsheet to calculate losses, and oh boy, in BCM, with something like 35A+ ripple current, even MPP would probably melt itself, and it almost did in my test. After a long search, I found something better than MPP: Kool Mu Hf. It's still much smaller than ferrite with no gap fringing etc issues, but at the same time better core losses than MPP. Still, BCM is not feasible at the power levels here, and most likely I will still have to deal with CCM/reverse recovery. In any case these cores seem to be even more efficient and smaller than MPP, which is not something I thought was possible!

Control/compensation of outer voltage loop:
The controller that I made is a simple PI loop with a feedforward term that makes the whole plant a simple 1/s integrator. I.e. a current source into a capacitor. This works great, although the constants were found experimentally, and I would like to get a better understanding of the tradeoffs when it comes to inductor/output capacitor selection for better control.

EMI/noise issues:
The way these FETs are cooled is a heat spreader in PCB copper on bottom layer, about 4in^2 on the drains, including one that is the switch node. Unfortunately that would make the entire heatsink oscillate at 50kHz/50V or whatever due to capacitive coupling. Adding some Y-caps to connect heatsink to the PCB GND made it better, but still lots of resonance existed. Adding some nanocrystalline beads around one or 2 of the Y-cap legs fixed this. Never thought EMI could be a real problem, but there it is! Lots more work needs to be done to make the fault/overcurrent circuit not react to small transients and latch the whole thing off. In future PCB, that heat-spreader doesn't need to be 4 in^2 either, less capacitance would mean less problems.

Anyway, this is still "early" on, and there are plenty more experiments to make. Once I reach the goal of 95% efficiency at 300W, and it being capable of 600W temporarily, I'll move into the next pieces of project (isolated input 200W MPPT, and an integrated lithium pack+BMS). The next steps/ideas are:

• Tapped inductor boost. Leakage inductance and control challenges here.
• better SiC switches (40mOhm instead of 80mOhm)
• fixed frequency current controller (a big one)
• isolated high-side gate driver supply to work around the bootstrap issues.

Any comments would be welcome!

[uer166]

Some more pics of the Kool Mu Hf inductors, efficiency, lowside Vds during high-side reverse recovery, and the first ever attempt an an (unstable) voltage control loop.

[uer166]

And here is the split-phase output and the nice hysteretic current control (blue trace is the current sense from the INA240).

[uer166]

About 2% efficiency gained by replacing low-side FETs from UF3C065080B3 (80mOhm) to UF3C065030B3 (30mOhm). I was hoping for a bigger difference but I suppose the high-side ones are still 80mOhm.

I'm realizing more that both high current and high voltage switching means it's very hard to optimize switches to something with low Rdson..

[capt bullshot]

Pretty interesting topology. AC output is (common mode) offset to 48V GND, this might cause issues. Your step-up stages are synchronous, so for a first try one could run them without a control loop (just put out a sine wave synthesized PWM).

Most inverters I've seen use two stages: A (isolated) step up converter to DC-link voltage and some H-Bridge for the output.

[uer166]

Pretty interesting topology. AC output is (common mode) offset to 48V GND, this might cause issues.

Ah, the "GND" in the schematic is more of a battery negative reference terminal. In reality, the entire battery and inverter will sit in a metal enclosure that is isolated from the schematic GND. The PE terminal at the outlet will only be connected to the enclosure itself, and it'll float relative to the inverter/battery. For bonus points can add an isolation monitor..

[uer166]

Here's a question for coupled/tapped inductor aficionados, what is the best construction method to minimize leakage inductance on a toroidal coupled inductor? So far I've made one with a 15 strand, each 28AWG, twisted/interleaved bundle coupled inductor. 10 strands are primary and 5 strands are secondary, 1:1 ratio since they are, can you say, a quindec-filar construction??

The results are: 48uH primary inductance with secondary open, and 145nH with secondary shorted, so a ~0.997 coupling factor. Is this a good number or is it possible to push it? Also, the leakage inductance measurement seems to go way up at lower (<10kHz) frequency, why is that? What I really need is to calculate the stored energy in the L_leakage during turn-off, but since it varies with frequency it seems to be non-linear, which is surprising to me.

Attached are some Bode 100 shots of the primary leakage and magnetizing inductance, and the construction..

[T3sl4co1l]

More interleaving is lower LL, yup.

It's also higher Cp.  What you're really after is getting Zo of the transmission line close to (within some factor, usually above) the peak switching impedance.  Since, at the instant of turn-off, peak switch current is transferred to the secondary through leakage, and switch voltage swings to whatever the nominal peak is, plus some overshoot.  The overshoot is due to LL, and if Zo = Zsw (and assuming t_sw << t_line*) you'd expect the peaks to be equal, i.e. total peak is twice the nominal peak turn-off voltage.

Likewise, at turn-on, switch off-state voltage is turned into switch current overshoot, by the same ratio.  You want Cp low for this, by the same ratios and for the same reasons.

Best is to get t_line << t_sw.  This is the old rule of thumb (minimize stray inductance), but actually meaningful as it considers LL and Cp together.  If you can't manage that, and can't afford to increase t_sw due to pressure from losses/efficiency, then you can add snubbers to dissipate (or sometimes return to the supply, in the case of quasi-resonant or active snubbers) that reactive energy.

*Electrical length of the transmission line, wire length divided by propagation velocity.  Which for twisted enameled wire, will be in the range of 0.6-0.8 c_0.

Note that any snubbers need to be "closer" to the active device, than whatever reactance they're snubbing.  This can be challenging with THT parts: even an SMA size diode is a good 5nH long, a 1210 chip capacitor is about 3nH, and a TO-220 device is another 7.5nH.  It's between impractical and impossible, to snub an inductance around 20nH.  (It might actually pay to increase loop inductance in such a case -- again, assuming loss/efficiency is fine.)

The other option is to simply divide up the power stage, so that each piece carries only as much current as it can safely handle.  Note: inverters can't generally be wired in parallel, there will be sharing issues.  So if you go the multi-channel route, plan on taking it to its full conclusion: independent (current mode controlled) channels, phase interleave.  Takes more parts, but ~infinitely scalable and can run that much faster (in turn saving on inductor or capacitor space) or at higher efficiency.


The discrepancy in measured LL may be due to skin effect?  Not sure if it should be that much, or if that's about right.  Anyway, skin effect means deeper penetration of magnetic field into the wire, means more space for it, i.e. LL is higher.  Resistance is also lower for the same reason.  This can be modeled as a diffusion resistance (an element which has equal parts inductive reactance and resistance, i.e. phase = 45 degrees, and Z ~ sqrt(F)).

Which... for a 5x frequency range, sqrt(5) ~= 2.31, or a bit over double the ACR.  Which is just about spot on, actually, which tells us we're above the skin effect cutoff for this wire (and could benefit from using finer strands).

Note: we can't use the same proportion on total inductance, because not all the magnetic field is in the wire, it's also in the space between wires!  We can consider LL as a sum of leakage through space (where mu_r = 1), plus the contribution from the wire.  The amount of inductance corresponding to that resistance change, is evidently delta j83mΩ reactance, or -26nH at 500kHz.  -25 was measured, which sounds pretty damn good, actually.  Nice.

Mind, for a constant inductance, inductive reactance is proportional to frequency; this reactance is sub-linear, so the inductance is decreasing (L ~ 1/sqrt(f)).  So we pick up the negative sign that way.

Modeling of this sort is fairly standard, if you'd like further reading consider this:
https://www.seventransistorlabs.com/Calc/Coilcraft1.html

Tim

[uer166]

Best is to get t_line << t_sw.

Interesting take on it, that rule of thumb seems quite useful to estimate t_sw. So if in my case, length of the transmission line is about 0.5m, and assuming velocity factor of 0.7, then t_line = 0.5/(0.7*c) ~= 2.5ns. I measured my current switching transition at around 10ns, I suppose that is in the same order of magnitude and I'd be better off increasing t_sw..

Increasing switching time of a SiC is not too easy, it wants to go fast, even with generous gate resistance..

[T3sl4co1l]

Current and voltage slew rates can be slowed with source inductance, and G-D capacitance, respectively.  Use a lossy element (L || R or R + C) to avoid ringing or oscillation.

Which is why you sometimes see ferrite beads on the gate or source terminal.  This isn't ideal, as beads typically saturate above a few amperes.  So, the snubbing behavior only shows up at low currents, just as the transistor begins to turn on, or finishes cutting off.  That may still be beneficial, depends.

Ferrite beads also aren't great for high power and high frequency, where they can literally cook from dissipation.  NiZn ferrite has a lower Tc and will self limit (with the result that EMI looks good for some seconds, then fades in real nasty), MnZn ferrite may cook surrounding things (e.g. glue used to hold it in place) before reaching that point.  (True story, I once demonstrated this with NiZn (#43) beads on the gates of modest sized MOSFETs, running at 2MHz.  They made great gate resistors, but got rather hot at that rate. )

Also, SiC?  At such low voltages?  What for?

Tim

[uer166]

SiC seemed to be the only option for low Rdson (30mOhm or so in a D2PAK), and low reverse recovery charge/losses. The 650V rating is incidental, I just haven't found any Si transistor with such low Qrr at given Rdson.

[uer166]

Here's a recently learned lesson: in a tapped boost, the switch node voltage on secondary side goes negative during on time to -Vin/N (or -48V in my case). That is bad news for the bootstrapped secondary-side FET, because then during that time, the secondary-side gate Vcc charges to 48+15=63V, when it should be 15!

Thankfully, the hardware overcurrent latch kept triggering within 500ns or so since this essentially looks like a short circuit to the inductor, and it saved everything except the gate drive IC (the high-side part)  .

[T3sl4co1l]

Ah yes, that would be important... 

Also on the schematics posted above, noticed the high side source node isn't labeled, so it doesn't seem to be connected to the driver either.

Tim

[uer166]

My bad, it's actually connected by net name but I forgotten to add a label to show it.. I wish diptrace had better facilities for net interconnects but oh well, at least it's very simple to use.

[gae_31]

helloo ,
Very interesting topic!

What is the idea of the tapped inductor? Is it a way to control the di/dt to divert the current from the rectifier at turn off?

I noticed that your current signal going to goes close to U1 through the 1k R11 and then it travels to input of the MCU where you have C32.
It might not be wrong, but you might pick some noise up along the way. So, I would actually have both R11 and C32 close to the MCU.

And about the magnetics: did you consider a gapped ferrite core with low core loss such as N97 in BCM. As you stated that would eliminate the reverse recovery issues.
The challenge would be obviously the winding loss in the inductor assuming that you can keep the peak-peak flux low.

[uer166]

What is the idea of the tapped inductor? Is it a way to control the di/dt to divert the current from the rectifier at turn off?

I noticed that your current signal going to goes close to U1 through the 1k R11 and then it travels to input of the MCU where you have C32.
It might not be wrong, but you might pick some noise up along the way. So, I would actually have both R11 and C32 close to the MCU.

And about the magnetics: did you consider a gapped ferrite core with low core loss such as N97 in BCM. As you stated that would eliminate the reverse recovery issues.
The challenge would be obviously the winding loss in the inductor assuming that you can keep the peak-peak flux low.

Hello! Yes, you're absolutely right, that "filtered" current sense trace did pick up noise along the way, I had to reduce the 1k to 100Ohms and add capacitor at the hardware overcurrent comparator, to have it not trip from noise. In the future, the source (INA240) needs to be low-impedance, and RC filter at each receiving end (at MCU and at overcurrent comparator). I think that would fix it.

As for the magnetics, I have indeed tried ferrite, the issue is:

• Size: it's much bigger than a powder core for a given DC flux/saturation rating. In my case the peak DC flux is very high since it needs to output sine wave peaks at a very high boost ratio. The brickwall saturation of ferrite is quite dangerous too for development.
• Fringe field heating: I would need a 4mm gap or so in ferrite, and in my quick experiments it heats up quite a bit

I think it could make sense, I need to do more testing. The other issue with BCM is it can't do multiphase interleave readily, and that is the plan for next revision: 2 sets of 2 phases, 180-degree interleaved.

Re: tapped inductor: it allows to be closer to the 50% duty cycle at higher boost ratios, reducing RMS currents, but more importantly it can reduce the peak voltage on the low-side FET, enabling the use of a 250V, or even 200V Vds FET that are ~10mOhm instead of ~30mOhm. Due to high I^2R losses, reducing the Rdson helps greatly. The high-side FET will need a high Vds rating still but that one sees less current.

I have the inverter phase 1 setup as the tapped inductor, the efficiency dropped by ~0.5% with everything else being equal, but it requires some supporting designs to push it beyond current efficiency (better windup, higher coupling coefficient, lower Vds rated low-side FET, maybe active clamp/quasi-resonant snubber).

[sandalcandal]

Hello uer166

This looks like a really interesting project and one relevant to my own interests so I'm keen to see how it progresses. No personal first-hand solutions to your challenges but I've seen some ideas you might want to try.

Bootstrapped High-Side Power
Some designs I've seen using bootstrapped power supplies solve this by having a pre-charge stage during their start-up/soft-start sequence.

This should be relatively easy to implement since you're using an MCU controller. Although not as simple as in the full-bridge example above where you can just leave a high side FET off while turning on the low side. You could keep the gate driver disabled and use the body diode for rectification while soft-starting and lightly loaded to let the bootstrap charge past UVLO perhaps? Through it seems you've mostly solved that problem already. Not completely clear on how you're doing your control loop but you might be able to get away with not using SR at really low duty cycle i.e. low current?

Reverse Recovery Losses
The stuff I'm looking currently at is mostly ZVS and soft switching so not as well read on this but have you considered GaN eHEMTs? Actually comparable in price to or sometimes cheaper than similar SiC in my experience. If you can't avoid hard switching then it might be well worth it in order to reach your target efficiencies whilst keeping in CCM. These devices have zero reverse recovery (Qrr=0), they work more like a Schottky with a very high forward voltage when reverse biased whilst off. Only downside it they're limited to lower voltages (<600V) compared to SiC (>1200V) but that's not a problem for your application I think. Driving eHEMTs is also a bit different to garden variety MOSFETs.

Inductor Core Losses
If you switch to GaN you also potentially go to even higher switching frequencies without losing too much loss budget to switching losses which could allow you to reduce required inductance or otherwise reduce inductor ripple current and hence flux swings in your given core. There is some trade off which higher frequency flux swing also increasing core loss however so you might need to end up changing to a high frequency ferrite to see overall efficiency gains. For most of the modern high frequency stuff I've seen saturation isn't a concern when operating at high frequency so much as just sub-saturation flux swing losses causing overheating. Speaking of which I didn't see what switching frequency you're operating at.

Inductor Winding
Not quite directly related to your question of reducing leakage inductance but I saw an interesting winding strategy in an app note here (page 65): https://www.wolfspeed.com/crd-06600ff10n I've attached an extract of the diagram and explanation. The windings are done in two opposite sections to cancel radiated flux.


Low Rds(on) FETs
My own calculations looking at transistor related losses generally puts the highest Rds(on) and conversely lowest Coss and Ciss FET in each FET family I've looked at as being the best overall value. Halving Rds(on) at cost of doubling capacitances ends up with much less than halving the loss (sometimes even more loss depending on switching frequency) whilst doubling the cost in most cases. Some designs seem to preference just paralleling multiple FETs to using single lower Rds(on) FETs possibly for more effective driving and power dissipation? I'm not sure.

Tapped Inductor
With the tapped inductor idea I feel like you're getting quite close to just doing a flyback circuit. Going that route could easily open as many new problems as it solves however...

SiC seemed to be the only option for low Rdson (30mOhm or so in a D2PAK), and low reverse recovery charge/losses. The 650V rating is incidental, I just haven't found any Si transistor with such low Qrr at given Rdson.

You fundamentally won't find Si with lower or comparable Qrr for the same Rds(on) due to SiC having different physics with its wider band gap energy. Then you have GaN eHEMTs with Qrr=0 because the HEMT construction is fundamentally different to MOSFETs and there's no body diode. Also beware casode GaN transistors which are different from eHEMT and do have a Qrr.

[rubidium]

Nice work, but I was wondering if you considered any cascaded-interleaved DC-DC topologies that would allow you to implement the latest lower voltage MOSFETs having much lower Rdson. Some of these can be had with sub milliOhm Rdson and could possibly get efficiencies closer to your original design objective..
Jim