For a point-to-point link, double termination is *not* required.
For instance when only a series termination is used, the voltage step on the near side is half of the drive voltage, divided between the series termination resistance and the transmission line impedance. When the half voltage reaches the open unterminated endpoint, the voltage doubles back to the original drive voltage, and when that reflection gets back to the driver, it is absorbed in the series termination.
For a parallel termination, the driver drives the transmission line to the full voltage, which then would double at the end of the transmission line but the impedance into the parallel termination halves that back to the original voltage with no reflection. This is the method that TTL would normally use, but if the transmission line impedance is 50 ohms, then a special TTL driver like the 74140 or 74S140 was required to drive that low an impedance and product TTL levels at the receiver. TTL usually worked with transmission lines of 100 to 150 ohms so this was not a problem.
That leaves some options. For highest performance, I like hacking up a custom driver using a couple of transistors to drive the transmission line with a current that has a defined voltage compliance producing the correct logic level and no aberrations, but that is not required here. (2) An HC or AC CMOS gate will drive a 50 ohm transmission line with a series termination of about 25 ohms to produce a 5 volt signal. Put several gates in parallel for better reliability (1) and increase the series resistance for the proper termination impedance. Double termination under this condition will produce a 2.5 volt high, which is technically high enough for TTL, but barely.
2.5 volts into a 50 ohm parallel termination will require 50 milliamps while 5 x 7404 hex inverters in parallel (the extra is used to invert the signal making the driver non-inverting) will only provide 25 milliamps, so a 7404 with parallel termination will not work, at least with a 50 ohm transmission line. A series termination will work though, but can you count on the receiver not being terminated?
(1) Divide the current up between parallel gates because CMOS has pin limitations on current, so pulling full current from one gate may be unreliable.
(2) If I did not use some gates in parallel, I would do it with a two transistor PNP current mirror that has maybe 10x current gain. This inverts, so drive it with an inverting gate or add a third NPN transistor inverter. The gate or open collector output drives the input to the PNP current mirror with a resistor which sets the input current, which is amplified by the current mirror, which pulls the transmission line up to about 4.5 volts. Parallel terminate the driver side and it should not matter if the other side is terminated or not, but set the driver output current to assume both sides are parallel terminated.