Logic-ICs - die pictures

[D Straney]

Interesting contrasting the layout of these older parts against some newer TTL, just in compactness - here's a 74LS00 and 74LS107, from a hybrid module with a late-90's date code.  You can see that by this point, with 7400-series ICs being a commodity item, they were really trying to squeeze the layout as small as possible on the 7400!


(The '107 is also interesting because it has a "73A" written with doping but a "107A" on the metal layer - these are both dual JK-FF parts, and I'd originally thought it was a 74LS73, except that the external connections didn't make sense with its pinout.  Makes me wonder if as part of that cost optimization, the manufacturer managed to use most of the same process for both of them, just with different metal layers?)

[Noopy]

It´s really funny to see how much silicon area they used back in the days. Today you can built a high performance mikrocontroller on this area.

The logic families for sure had a high cost pressure.

[D Straney]

Don't want to step on your thread here, but here's some other digital logic I ran across recently, from a mystery hybrid on a Rocketdyne board.  They all look like SSI/MSI CMOS of some kind.

This one's interesting because the structure looks very "new", as in, taking full advantage of high process resolution.  Rather than each transistor (or diode) being a single easily-identifiable source-gate-drain structure, it's a conglomeration of individual tiny devices, kind of like the way modern power MOSFETs are made.  At least that's my interpretation - please correct me if I'm wrong:


These two are much more "traditional-looking", but I still have no idea what they are.  The 1st has some very large transistors (might be a 4x analog switch actually, like the 4066?  Oops), and the 2nd could be a multi-bit register or mux of some kind?  It looks like there's a common set of 7 control lines in the center, which run up on the left, loop around at the top, and come down on the right.

[Noopy]

Don't want to step on your thread here, but here's some other digital logic I ran across recently, from a mystery hybrid on a Rocketdyne board.  They all look like SSI/MSI CMOS of some kind.

That´s no problem for me. 

This one's interesting because the structure looks very "new", as in, taking full advantage of high process resolution.  Rather than each transistor (or diode) being a single easily-identifiable source-gate-drain structure, it's a conglomeration of individual tiny devices, kind of like the way modern power MOSFETs are made.  At least that's my interpretation - please correct me if I'm wrong:

To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. 

The second die could be a analog switch too or it is a gate driver.
The third die is a big analog switch or MUX.

[Noopy]

Texas Instruments always prefixes the designation of its logic components with the letters SN. The letter J is assigned to components that have been developed, manufactured and tested in accordance with the MIL-STD-883 standard. In contrast to the 74 logic, the 54 logic is specified for the military temperature range (-55°C to 125°C). AS stands for “Advanced Schottky”. The numbers 04 show that six inverters have been integrated here. FK stands for the package type.




Texas Instruments explains in “The TTL Data Book Volume 1” the difference between the logic families. The AS variant offers the shortest propagation delays.






The dimensions of the die are 1,4mm x 1,2mm. As usual for Texas Instruments, a Ti logo is shown on the die. In addition, the characters AS04 can be found to match the logic module. Special structures are superimposed in different layers on the bottom and right edges. They clearly show how well the masks were aligned during production.




The SNJ54AS04 uses two metal layers. The active structures are unusual. 


https://www.richis-lab.de/logic38.htm

 

[D Straney]

To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. 

Yes hah, by "modern" in this case I mean "newer than the 70's"....not actually very modern.  And that's an interesting comparison, thanks - although I'm not convinced this one is an analog switch.  In your analog switch die, only the actual analog-switch MOSFETs have the "compound" construction, while the other (control logic) MOSFETs are more standard single-piece lateral devices; in my mystery die, it looks like everything (including the ESD diodes) has the "compound" construction.

Every time I look at a die with no part number markings, it just makes me wish harder that there was a die-image-matching search engine.

Also, on that 54AS04, a lot of those alignment markers along the edge don't actually look well-aligned.  Do you know if that was a camera/imaging-setup artifact, or intentional, or if the layout can actually tolerate that much slop?  (The actual features look better-aligned than that, but I'm not an expert...)

[Noopy]

To me this part looks more like an analog switch (like this one: https://www.richis-lab.de/aswitch06.htm).
I wouldn´t say that it is a very modern process but that always depends on what you want to call modern. 

Yes hah, by "modern" in this case I mean "newer than the 70's"....not actually very modern.  And that's an interesting comparison, thanks - although I'm not convinced this one is an analog switch.  In your analog switch die, only the actual analog-switch MOSFETs have the "compound" construction, while the other (control logic) MOSFETs are more standard single-piece lateral devices; in my mystery die, it looks like everything (including the ESD diodes) has the "compound" construction.

Hm, I took a second look at the image. Now I don´t think any more it´s an analog switch. It seems these are Highside-/Lowside switches at the output.
Six inputs, eight outputs, the part in the middle looks like an adressing. Perhaps it´s a shift register.

Every time I look at a die with no part number markings, it just makes me wish harder that there was a die-image-matching search engine.

Either this or an AI circuit recognition tool. 

Also, on that 54AS04, a lot of those alignment markers along the edge don't actually look well-aligned.  Do you know if that was a camera/imaging-setup artifact, or intentional, or if the layout can actually tolerate that much slop?  (The actual features look better-aligned than that, but I'm not an expert...)

In my view the alignment is not bad (for the big structures). As far as I know these alignment markers are built like caliper: They should not lay above each other and show a small horizontal misalignment very clearly (vertical on the right).

[Noopy]

The Texas Instruments SN7400 shown here was produced in 1970. It is packaged in a so-called flat package, a metal housing in which the pins are led straight out to the side. One contact has a protruding element that identifies pin 1. The transport frame is known as a Mech-Pak carrier. A piece of Kapton is glued to the underside.




With the different SN5400 and SN7400 variants, it is important to note that the pin assignment is not always the same. Texas Instruments shows this in “The TTL Data Book for Design Engineers - Second Edition”. The SN54L00 in the “flat package” (T), the SN5400 and the SN54H00 in the “ceramic flat package” (W) expect their supply voltage at the pins in the center of the package, not at the opposite corners. In addition, the lower gates are rotated by 180°. The SN7400S contains the right-hand architecture, but is so old that it is no longer mentioned.




Glass insulates the pins from the metal housing. The cover is welded onto the housing.




Inside the package, you can see that the pins on the sides are literally molded in glass.




The dimensions of the die are 1,5mm x 1,3mm. It is therefore significantly larger than the newer generation (https://www.richis-lab.de/logic14.htm). Some auxiliary structures are shown in the corners, which make it easier to place the masks appropriately and monitor the manufacturing process.

The design does not yet include protection diodes at the inputs. The input transistors of each gate have four emitters. This means that NAND gates with up to four inputs can also be implemented with a different metal layer. Although no passivation layer is visible, there are no metal surfaces on the unused emitter contacts. It must be assumed that these contacts are exposed. This entails the risk of contamination entering the active area.

The HFO D100 (https://www.richis-lab.de/logic31.htm) is quite similar to this SN7400S...




Texas Instruments shows a picture of the SN5400 specified for higher temperatures in a 1965 datasheet. From there to the die we have here you can see a certain evolution. The large transistors and the arrangement of the elements are very similar but not quite the same.


https://www.richis-lab.de/logic39.htm

 

[RoGeorge]

Wow, never seen that red thing before. 
The name suggests its purpose was for storage, but the wider golden strips at the sides makes it look like a socket. 

Is that wider golden end of each pin because that is a socket, or is it wider because the pins were not yet cut/separated from the metal frame?

Then, the shape of the red plastic looks too elaborate to be just a storage/protection package, looks like it was made to fit with something else.  Was it the equivalent of today's reels/feeders for automated assembling machines?

So, what for was that Mech-Pak carrier?

[AnalogTodd]

The packaging on this is not your normal garden variety package used in everyday applications. This is for special high-reliability applications like radiation hardened and space. The package is NOT cheap. In today's dollars, your normal J/N packages (the old ceramic dips you're used to) would cost under a dollar. This package would cost probably $20-30. The overall part cost for your garden variety commercial/industrial units would be cheap compared to this. Think of 2$ compared to 200$. These parts aren't sold in million piece quantities, they're ordered maybe in the hundreds at a time.

The glass insulation of the pins from the housing is to completely seal the package against any leaks of liquids or gas. Even hydrogen gas getting into the package in these environments can be very detrimental to the die. Units like this have to go through specialized leak testing before shipment to the customer.

The Mech-Pak carrier is meant to protect the pins from potentially being bent as the part is handled from assembly through test and shipping until the customer installs it on their board. It is meant to interface with the test system so that the part would not need removed from the carrier for test.

There is a reason you don't see any passivation on the die as well. Passivation usually included a PEN (plasma etched nitride) step over the normal silicon dioxide. The issue is that in radiation environments nitride will trap charge much more than the normal oxide and this would make the chip function fail at a lower radiation level.

Any other questions?

[Noopy]

Thanks for adding all the information. 

There is a reason you don't see any passivation on the die as well. Passivation usually included a PEN (plasma etched nitride) step over the normal silicon dioxide. The issue is that in radiation environments nitride will trap charge much more than the normal oxide and this would make the chip function fail at a lower radiation level.

But why didn´t they put a metal square on top of the unused emitter contacts?

[AnalogTodd]

But why didn´t they put a metal square on top of the unused emitter contacts?

That's a good question I can't answer offhand. As an IC designer, my first inclination would be that ALL contacts must be covered by metal to ensure nothing can get into silicon junctions.

[Noopy]

The SN7404 contains six inverters. Like the SN7400S, the SN7404S is placed in a flat package suspended in a Mech-Pak carrier. This part was manufactured at the end of 1969.




As with the SN5400 and SN7400 variants, it is important to note that the pin assignment is not always the same. “The TTL Data Book for Design Engineers - Second Edition” shows us the difference. The SN7404S contains the right-hand architecture, but is so old that it is no longer mentioned.




The edge length of the die is 1,5mm. The six inverters are clearly visible. Extensive auxiliary structures can be seen in the corners. A test transistor has been integrated at the top edge.

The design has been optimized a lot im comparison to the newer SN7404: https://www.richis-lab.de/logic16.htm




The input transistor in the bottom left-hand corner has a large base area, which would provide space for several emitters and therefore several inputs. However, these additional emitters are missing here. The resistors offer several alternative contacts that make it possible to set the operating points of the individual stages of the inverters.


https://www.richis-lab.de/logic40.htm

 

[Noopy]

One more SN74xxS. The SN7420S contains two NAND gates with four inputs each.




Remember, the pinout is different than "today".




The edge length of the die is 1,1 mm. The two NAND gates are clearly visible. The inputs end in the familiar large transistors with four emitter areas.


https://www.richis-lab.de/logic41.htm

 

[Noopy]

SN7474S with two flip-flops in the flat package and the Mech-Pak carrier we have already seen.




Be careful with the pinout!




The edge length of the die is 2,0mm x 1,5mm. The flip-flops are arranged symmetrically around the center.


https://www.richis-lab.de/logic42.htm

 

[AnalogTodd]

Somehow you've managed to find a trove of high-rel parts somewhere! I know companies often just bin leftover units because they often have some remaining after production, but given the cost usually involved on these parts (not to mention the smaller order quantities) that's a lot more rare.

[D Straney]

A surprising number of these actually pop up on eBay (for example, https://www.ebay.com/itm/126980467234, or search "gold flatpack IC").  My only guess for how the NOS stuck around for so long is as military spare parts for old aircraft computers, etc. where they wanted a stock of spares always on-hand at repair depots.

[Noopy]

I got these as a small lot from Ebay. One is left.

But I have also some more modern MIL logic here.

...and I will get a cool lot of parts that were used in the Giotto mission: https://en.wikipedia.org/wiki/Giotto_(spacecraft) ...of course not the parts that were on the mission. 

So much to do... 

[Noopy]

The Harris Semiconductor CD74HCT14 contains six inverting Schmitt triggers.




The edge length of the die is 1,6mm x 1,1mm. 13685A could be an internal project designation. The six Schmitt triggers are clearly visible.

This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/57x02XL.jpg (22MB)




The damage to the thinner wire was probably caused by the decapping. The cause of the dark artifacts on the thicker line remains unclear.


https://www.richis-lab.de/logic43.htm

 

[Noopy]

The Schmitt trigger in the bottom left-hand corner is used for a more detailed analysis.

This image is also available in a higher resolution: https://www.richis-lab.de/images/logic/57x04XL.jpg (24MB)




In CD74HCT14, the NMOS transistors are located in p-doped wells. The substrate is n-doped. The frames of the NMOS wells are partially visible. In line with this, the frame structure of the die carries the Vdd potential rather than the GND potential.




There is a protective structure at the input of the Schmitt trigger. The resistor R1 limits the current flow into the circuit. The diode D1 cuts overvoltages. This is followed by an element whose function is not self-explanatory. It appears to be an NMOS transistor that lacks the typical gate electrode. In the right-hand area, the metal layer is slightly wider and could act as a special gate electrode. MOSFETs that use the field oxide as a gate oxide are often used in protective circuits. This special feature increases the threshold voltage, making the MOSFET conductive much later and making it more suitable for overvoltage protection. The circuit itself is known as a grounded gate NMOS. Such a MOSFET becomes conductive with ESD pulses and negative voltages. The MOSFET also represents a certain resistance as it is looped into the line. This measure presumably improves the behavior with ESD pulses with large gradients. A small contact can be seen at the end of the protective structure, which is apparently another diode.

The circuit at the input of the CD74HCT14 is relatively complex as it has to represent the hysteresis of the Schmitt trigger. Two PMOS transistors are connected in series on the Vdd side. On the GND side, there are even four NMOS transistors in a series and parallel circuit. The transistors M9, M13 and M14 are controlled via the output of the stage. They intervene between the series circuits and thus form a feedback loop. This results in the desired hysteresis.

Four inverter stages are following. The areas increase steadily up to the large output stage transistors. The high number of inverter stages increases the delay of a signal, but it is necessary so that the gate electrodes of the large output stage transistors can be recharged quickly enough. The M12 transistor forms a further feedback loop around the M10/M11 inverter. The unused PMOS transistor M15 is also located in this area.


https://www.richis-lab.de/logic43.htm#schematic

 

[RoGeorge]

Wow, the high-res picture looks astonishing in full screen! 
Stare at it for too long, and now I have so many questions.

-1.  Was the chip functional?  Asking because the metal traces looks fractured many times, from one edge to other, particularly in the most wide traces.  Are those crack-lines going deep enough into the metal layer, so to interrupt its continuity?


-2.  Another thing, trying to match the die pics with typical CMOS gate structures in TI application notes.  This one is about the MOSFETs area ratio:  https://www.ti.com/lit/an/scla011/scla011.pdf

HC vs HCT input MOSFETs area - Fig.6 from scla011 pdf - TI

The threshold voltage of a CMOS circuit is determined by the geometry of the input transistors. These transistors are designed to sink the same input current at the required threshold voltage. The resulting voltage at the output is equivalent to 50% of the supply voltage VCC . For an HC circuit, the channel width of the p-channel transistor of the input is approximately twice the value of an n-channel transistor. The purpose is to make both transistors have the same current characteristics, thus making the threshold voltage of their input at about 50% of the supply voltage VCC . This circuit area has been modified for HCT devices: the n-channel transistor is about seven times wider than the p-channel transistor (see Figure 6). This shifts the threshold voltage in a way that it amounts to 30% of the supply voltage. At a supply voltage VCC = 5 V, the threshold voltage is VT = 1.5 V, similar to the threshold voltage of TTL circuits.

The area ratio was easy to confirm for the output MOSFETs:  M22 on the die (or M20 in the schematic, I guess that's a numbering typo) is indeed about twice the size of the M21 (same as the HC series would require for its input MOSFETs, because the output of HCT series has a symmetric characteristic of N vs P channel MOSFET).

Now, for the input MOSFETs of this 74HCT14, the area ratio has to be about 1:7 for P vs N channel MOSFETs, according to the same Fig.6 above.  In the schematic, there is (M7+M8) for P channel, and the parallel (M2+M3) || (M4+M5).  So, the area of (M7+M8) vs (M2+M3) should be about 1:3.5, did I got it right so far?

The question is:  When looking at the annotated dieshot, M3 seems to be made of 2 identical structures in parallel.  Is M3 (on the die) made out of 2 parallel MOSFETs? (same question for M2).  Asking because my skill of identifying transistors on a die are practically zero.


-3.  Another question, you say one can almost see the doping wells.  How visible is that, or how to recognize the wells borders?  Is it the green thing in the high res pic?

Asking because I'm trying to match the die layout with this expected layout from Figure 15 in https://www.ti.com/lit/an/scla007a/scla007a.pdf :




One page before Fig.15 above, the TI AN describes 2 possible types of ESD protection.  Would be interesting to see how much of that can be matched with this 74HCT14 die, particularly since this model is a rad-hard chip (doh, my bad, I notice now this 74HC14 is a normal DIL14, no Mech-Pak carrier).  I have another set of questions about that, but this post is already too long.

[harerod]

Noopy, as always, thank you for your effort!
Those old Lattice chips bring back memories. Back in the mid-1990's, as a side job while still in engineering school, I helped an industrial client with the design of an arbitrary waveform generator. The device contained some interesting chips for that time, e.g. a programmable PLL, dual ported SRAM and an HDPLD.
"The global routing pool is full" is something that has been edged into my memory.
Back then, a digitally programmable PLL was interesting enough for a short oral recitation at school. An effective algorithm for automatically finding the parameters for a required waveform prepared me for setting up the clock system of STM32's.
At first, I had huge problems serially programming the parameters into the PLL. While assembling the prototype, I had used DIL sockets with integrated 100nF cappas - ready for TTL power supplies. Unfortunately, what was VCC/VSS on TTL, was DataIn and ClockOut for that PLL, whose vendor/type I can't remember. Tracking down that bug was a real experience. 

[Noopy]

Wow, the high-res picture looks astonishing in full screen! 

I really like my microscope objectives.  Here I used the UMPlanFl 50x 0,80 BD.

-1.  Was the chip functional?  Asking because the metal traces looks fractured many times, from one edge to other, particularly in the most wide traces.  Are those crack-lines going deep enough into the metal layer, so to interrupt its continuity?

I´m not 100% sure but I assume these are artefacts in the structure of the metal and not cracks. Aluminium should be ductile enough to withstand a lot of stress.
I don´t know if the chip was functional but I bought it on ebay as working.

-2.  Another thing, trying to match the die pics with typical CMOS gate structures in TI application notes.  This one is about the MOSFETs area ratio:  https://www.ti.com/lit/an/scla011/scla011.pdf

Interesting! 

Now, for the input MOSFETs of this 74HCT14, the area ratio has to be about 1:7 for P vs N channel MOSFETs, according to the same Fig.6 above.  In the schematic, there is (M7+M8) for P channel, and the parallel (M2+M3) || (M4+M5).  So, the area of (M7+M8) vs (M2+M3) should be about 1:3.5, did I got it right so far?

Yes, should be right.

The question is:  When looking at the annotated dieshot, M3 seems to be made of 2 identical structures in parallel.  Is M3 (on the die) made out of 2 parallel MOSFETs? (same question for M2).  Asking because my skill of identifying transistors on a die are practically zero.

You could say that in M2 there are four MOSFETs. Every greenish gate electrode is one MOSFET. Left an right of the gate is drain and source and the MOSFETs are sharing them.

-3.  Another question, you say one can almost see the doping wells.  How visible is that, or how to recognize the wells borders?  Is it the green thing in the high res pic?

Asking because I'm trying to match the die layout with this expected layout from Figure 15 in https://www.ti.com/lit/an/scla007a/scla007a.pdf :

In the TI picture you see two wells in the CD74HCT14 you have just a well for the NMOS like you can see it here:
https://toshiba.semicon-storage.com/eu/semiconductor/knowledge/e-learning/cmos-logic-basics/chap2/chap2-4.html

Look at M3 on the left side, left of the metal trace you can see the edge of the well. As soon as you have recognised this edge you can find more of them. But you can´t see every well edge and of course just at the NMOS transistors.

One page before Fig.15 above, the TI AN describes 2 possible types of ESD protection.  Would be interesting to see how much of that can be matched with this 74HCT14 die, particularly since this model is a rad-hard chip (doh, my bad, I notice now this 74HC14 is a normal DIL14, no Mech-Pak carrier).  I have another set of questions about that, but this post is already too long.

The ESD protection TI shows is similar but not the same. At least I assume that this is the case. The grounded gate NMOS does not work like a normal MOSFET. When there is an ESD pulse a parasitic bipolar transistor in its structures becomes conductive. The TI circuit adds a latching structure so it stays conductive. In my view the the structures in the 74HCT14 are to simple for such a latching circuit.

Now feel free to go on with the circuit analysis. 

Noopy, as always, thank you for your effort!

It´s a pleassure! 

Those old Lattice chips bring back memories. Back in the mid-1990's, as a side job while still in engineering school, I helped an industrial client with the design of an arbitrary waveform generator. The device contained some interesting chips for that time, e.g. a programmable PLL, dual ported SRAM and an HDPLD.
"The global routing pool is full" is something that has been edged into my memory.
Back then, a digitally programmable PLL was interesting enough for a short oral recitation at school. An effective algorithm for automatically finding the parameters for a required waveform prepared me for setting up the clock system of STM32's.
At first, I had huge problems serially programming the parameters into the PLL. While assembling the prototype, I had used DIL sockets with integrated 100nF cappas - ready for TTL power supplies. Unfortunately, what was VCC/VSS on TTL, was DataIn and ClockOut for that PLL, whose vendor/type I can't remember. Tracking down that bug was a real experience. 

Sounds interesting and very educational. 



EDIT: I corrected the M20/M22 typo. Thanks! 

[Noopy]

SNJ54S38, the Schottky-Variante des 5438 and of course the MIL variant. 






The dimensions of the die are 1,2mm x 1,1mm. Texas Instruments usually integrates a Ti logo. Here there is no such logo. The character sequence S38 refers to the 54S38 variant. As will be shown shortly, another variant can also be build on this die. The letter A could stand for a first revision.




The structures are still quite clear.




The base contacts of the transistors contact both the base and collector areas. A Schottky contact is created between the metal layer and the weaker n-doping of the collector, which makes the transistor a Schottky transistor. Such a transistor does not saturate and can therefore be switched off more quickly.




The individual elements of the circuit can be easily identified.




Three transistors and three resistors are not included in the circuit. These additional components can be used as an alternative to the 54S00. The 54S00 also contains four NAND gates, each with two inputs, but has a push-pull output.

It is noticeable that the resistance values in the datasheets of the 54S38 and the 54S00 are significantly different. This may be due to the fact that the datasheets describe different generations. If the specifications of the transistors change when switching to a different process, the resistors must also be adjusted. In addition, the exact resistance values are hardly relevant for the user and are subject to large tolerances. Accordingly, the datasheets indicate that these are only nominal values.


https://www.richis-lab.de/logic44.htm

 

[Noopy]

A minor correction:
The 54S38 contains four NAND gates with two inputs each and powerfull open collector outputs (they are buffers).
Because of that the related 54 variant is not the 54S00 (weak output) but the 54S37 (buffer output)!
Now the resistor values are more similar too.