Do you know how much filtering you actually need?
100uH is pretty large. Certainly large enough you need to account for its impedance, so as not to make the supplies "bouncy". Too high of an impedance into a switching regulator, at a low frequency, and you get an oscillator -- the regulator input is negative resistance (it doesn't need to draw as much current, at higher voltage, since it conserves power).
Note that a supply isn't just, you stick a filter on it and it's done. Filtering is with respect to a given connection. If the input isn't noisy, you might simply wire the 12V input to the output connector and that's that. The regulators are a pretty obvious source of noise, so it makes sense to add a filter between regulator input, and power input
or output. This is why I noted the 12V output is unfiltered: it carries full regulator ripple to the output.
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This would be the only filtration for 12v input rail, then I feed this into the switchers and remove the useless small value ceramic caps and only keep the 22uF ones in both input and output. While also keeping 47uF elec. caps for outputs and add one elec. 47uF + 22uF ceramic + Ferrite bead just before the 12v connector itself.
What do you think?
Yes, that sounds fine, or at least more reasonable; exact values still matter so it depends, but that should be in the right ballpark.
Again, ferrite beads amount to nothing; it's strange that they're even shown in the regulator datasheet at all, but it's also amusing that they label it as "10nH", i.e., as good as an equivalent length of wire (well, a cm or so).
If you know you need some actual output filtering, more like 0.1 to 2.2uH is probably reasonable, plus enough capacitance to get Zo low enough for required load step response, and well damped so it doesn't oscillate.
Zo = sqrt(L/C) is the characteristic impedance of an LC circuit. When Zo ~ R, the network is well damped. (Whether it's greater or lesser by a modest factor (say 1-2x), depends on how it's arranged.) Zo gives the step response, as a load step change of say 1A is expected to develop Zo*1A peak voltage change. If your output is say 3.3V 1A, and regulation must be within 5% including transients, then peak voltage must be under 0.165V for a full load step or 1A change, so Zo < 0.165Ω.
For 1uH and Zo < 0.165Ω, C > 36.7uF. This can be, for example, a 22uF ceramic in parallel with 47-100uF electrolytic, selected for ESR ~ 0.15Ω. Or the equivalent constructed from parallel ceramics and an explicit resistor.
Or if using just ceramics, since ESR ~ 10mΩ on those, you need Zo similarly low, say L around... 10nH? Well, I suppose that explains where that number came from. Note that 10nH and 22uF has a cutoff of 340kHz so will not attenuate much more than the sheer bulk capacitance is already doing. Which makes sense, the caps themselves have 2-3nH ESL so a 10nH in series between a few of them doesn't really mean anything, it's a pretty weak impedance divider, hardly a filter at all.
I wonder about those designs where people put various ceramic caps values in parallel, especially at output. like 22u, 1u, 100n, 1n... does this really enhance HF noise suppression?
At best, it's an outdated practice.
The ESL of a chip capacitor is essentially its package size. Period. It hardly depends on value, it doesn't depend on voltage, it depends a bit on height, and most of all it depends on the length and aspect ratio. (Which is why wide-body components are recommended for critical applications.)
The frequency of minimum impedance (series resonance) does depend on value, but the asymptote extending above there, is the same impedance -- the same ESL -- regardless of value.
So you get as good performance, beyond say 10MHz, with 0.33uF as with 33uF or anything inbetween.
Putting smaller caps in parallel, is likely to make things worse, due to the resonant loop formed between the smaller cap, its capacitance, and the larger cap. Such loops are on the order of 6nH, so for say a 10nF, you get Zo = 0.77Ω and Fo = 20MHz. The 10nF might have 100mΩ ESR, giving a Q of 7, or an impedance peak (parallel resonant equivalent, Zpeak = Zo * Q) of 5.4 ohms -- massively worse than the impedance of the bulk cap's inductance alone (which if it's 3nH, is only 0.377Ω at 20MHz).
And for switching regulators, it's not likely to do much of anything at all, anyway: the impedance is so much lower than for an individual logic IC for example. Say the peak voltage and current are 12V 2A, then the impedance needs to be much less than their ratio, or 6Ω. A small cap like 10nF just disappears, it does nothing, the input ESL dominates. Much better to put the bulk cap there, or at least a big enough bypass (typically 1uF) to dominate over the ESL to the next bigger cap (while again being chosen for ESR to dampen that loop!).
So a 1uF at each regulator, and one or a few 22uF nearby, is likely fine for your purposes. Plus whatever input filtering is needed, again dimensioned so that Zo is low enough, and with ESR provided to dampen it.
Using this scope at the fablab would be problematic due to the horrible noise floor (tested by shorting the probe to GND pins) of 50mV. Should I use CH1 to get power (3.3v, 5v, 12v) and CH2 for probing GND, then do subtraction in scope software? shouldn't this eliminate the noise floor?
I think I cannot go to market with this design if it is just slightly better than the best one available, I wanted it to be a lot better.
What? You mean the scope, probe disconnected, has a noise floor that high? It sounds defective.
If you mean with the probe tip grounded to its clip,
and this point connected to circuit ground, then that is probably typical of your circuit's common mode noise, and this is dropped across the narrow, lengthy ground return path around the regulators. And will likewise be emitted from the power cable, failing EMC.
They don't show the bottom layer in the datasheet layout example, but one should assume it's ground pour. They do show vias for this purpose. Strangely, they also show vias for VIN and VOUT, which have no business running on the bottom layer. It's not clear what they mean by that. Examples must always be taken as just that, examples; sometimes they're reasonable, sometimes they're cooked up by some random intern, who knows.
Another tip: avoid VIN and VOUT on opposite sides of the board -- this guarantees that, the full voltage drop across circuit ground, appears between connectors. Instead, place them adjacent where possible, and route the connections over to the regulators, off to the other side. This confines ground-loop currents to the regulator area. Routing VIN and VOUT away from that critical area, they can be filtered with respect to a more stable GND, with less voltage drop between their respective GND connections (namely, the filter cap GNDs).
Tim
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