Power MOSFET (gate) ringing/oscillation

[notadave]

I am frustrated with power MOSFETs >200V_DS. They seem to like to oscillate in ways that are "illegal" compared to the datasheet.
When I looked at old designs I saw that most had, in parallel with the Gate-Source, a series capacitor-resistor. I did not know why, what problem they were supposed to solve. Well, now I do.
There seems to be an oscillation during switching that is internal to the FET. From the outside it is most "visible" by measuring the gate voltage. I have observed it in the 30 to 100 MHz region.
Although the voltages clearly exceed the maximum ratings there is no immediate failure. Thus the question is: Does this even matter? Obviously my employer will not accept "It does not seem to fail when I am looking." as a guaranty this will not cause a recall or worse.
Does this have a name? The device manufacturers sure are not making an effort to point this out.
It seems that there should be a statement in most datasheets:
"This device requires external C_GS = C_iss/2 (half gate-capacitance) and R_GS = R_G (gate-resistance) for dampening to comply with the gate source voltage (dynamic) maximum rating."
"The negative peak of U_GS at the cut off after reverse recovery is exempt from the max. gate source voltage (dynamic) rating requirement."
I did catch this when I used a H near field probe to find the current path but could mostly find the signal around the device package not the PCB.

[Andy Watson]

... Does this even matter?

Yes.
The oscillation will disspiate excess energy in the transistor and create a lot of rado-frequency interference. Try listening to a FM radio near-by. Although, you are only seeing oscillation on the switching transitions there is a chance that in unfavourable conditions and a source of energy, the ringing could develop into full, sustained oscillation.
The problem arises due to the inductance of the leads and the capacitances in the MOSFET and surrounding circuit. The solution is to spoil the Q of the inductive-capacitive loops, usually be including a resistor in series with the gate. Note that using just a capacitor alone between gate and source will make it worse (it increases the Q). Look-up grid-stopper resistors.

[mtwieg]

Are you using the FETs in a hard-switching application, or are they biased in saturation (like a linear amplifier)? If hard switching, ringing on the gate can be due to the gate drive transitions being underdamped, or the FET itself being unstable during the switching transition. If the switching transition is very fast, then the oscillation shouldn't persist long enough to do any damage (but might be an issue for radiated emissions).

For linear operation on the other hand, snubbing circuits like this are often necessary, especially if the FET packaging has significant lead inductance.

Could you share a schematic of the circuit you're troubleshooting?

[AnalogTodd]

As was pointed out, you have a capacitance which is the gate-source junction of the MOSFET. Any trace, wire, or package lead will have inductance (a typical rule of thumb is 30nH per inch) and driving this L-C combination directly will cause oscillations. A simple simulation of a pure L-C circuit driven by a step will show a waveform at the center point that is twice the amplitude of the step input at the resonant frequency of the L-C. It's a very high Q tank circuit.

As already said, using a resistor in series with the gate will lower the Q and control the ringing.

[stretchyman]

Short leads + non inductive res.

If half bridge add a snubber too.

I'm switching at 200KHz (half bridge pwm) and all is well.

[notadave]

dissipate excess energy in the transistor

True, but does not seem to be a thermal problem.

radio-frequency interference. Try listening to a FM radio near-by.

Good idea, I always wanted to, but never remembered, my colleague has a 35 year old one that does all bands.
We did EMI measurements, I can check the results against the frequency I observed.
BUT I did mention that the oscillation is actually local to the device, it does not propagate.

into full, sustained oscillation

That is not the case. I'll come back to this below.

The problem arises due to the inductance of the leads and the capacitances in the MOSFET and surrounding circuit. The solution is to spoil the Q of the inductive-capacitive loops, usually by including a resistor

THAT does not seem to be the entire story. There is something going on inside the FET.

using just a capacitor alone between gate and source will make it worse (it increases the Q)

I know people who actually did that and found out. In one configuration they did manage a large oscillation that was sustained for about 100 ns.

[notadave]

If hard switching, ringing on the gate can be due to the gate drive transitions being underdamped, or the FET itself being unstable during the switching transition.

I can't prove it but I think it is the later.

If the switching transition is very fast, then the oscillation shouldn't persist long enough to do any damage (but might be an issue for radiated emissions).

That seems to be the case.

Could you share a schematic of the circuit you're troubleshooting?

It is so simple that it is not worth putting up here. We are talking about a switching half-bridge with resistors between the gate and driver.

[mtwieg]

It is so simple that it is not worth putting up here. We are talking about a switching half-bridge with resistors between the gate and driver.

Would be useful to at least get a sense of the component values, switching speeds, and parasitics involved. A photo of the PCBA might be helpful as well.

It's possible that putting snubbers on the switching node or across the DC bus might also reduce the ringing you observe on the gate.

[notadave]

component values: 600V n-MOSFET
switching speed:   40 kHz with PWM
parasitics involved: TO-247 Package, there is some inductance between the half bridges but the rest is small
Gate resistors:       27 Ohm

snubbers on the switching node

I did consider that but every time I did the math the power was too high.

the DC bus might also reduce the ringing you observe on the gate

I also observe it drain to source but it is much harder to see with the switching, high voltage, other oscillations. The thing is that I could not find the current outside of the package.

[notadave]

or the FET itself being unstable during the switching transition.

That is the topic. I think mine and possibly many others are.

[ahbushnell]

What gate resistance are you using?  We use SiC MOSfets and we always make sure we can change the gate resistor value.  The low limit in the data sheet almost always gives us ringing problems. So we end up increasing the gate reisitor value to fix this problem. 

[multipla]

Can you show a picture of your layout, between the gate driver and the MOSFET?

[notadave]

I appreciate your help!
But I am not here to talk about:

• Layout
• R in series with gate

I am here to talk about vertical power MOSFET devices and a specific phenomenon.

I did not become more explicit because I did not want to push the discussion towards a particular conclusion. I wanted to see if others recognize the problem.
What I am observing may be known as: Common source inductance induced gate oscillation
On this forum I could find: Post
Yes, the outer circuit will have it's role.
The mechanism might be:
The reverse recovery causes a huge di/dt and thus a negative voltage spike over the L_S.
That voltage is part of U_GS causing the gate to measure a huge negative voltage, that is not over the gate isolation.
The spike does disturb the gate driver to gate loop.
The following oscillation is poorly dampened by the low gate resistance. There is a huge current over C_GS, that does not flow through R_G.

[multipla]

The simplest explanation might be that the layout is bad and introduces too much inductance which then oscillates with the input capacitance. Your source inductance is part of that circuit. That is simple physics and something that can get really bad if you did not think about it during layouting.
I would check this first.
It's all in the layout, there is no magic oscillator in the gate of the MOSFET.

[stretchyman]

So I'm switching @ 200KHz and don't have any issues but not without earlier design issues.

Depends on the FETs (Qg mainly?) and the layout.

Some half bridge drivers have the output pins in a silly place so you have to 'rotate' the FET to get the input pin close.

No mention of what FETs you're using, the half bridge driver chip or any image of the layout, all are critical.

Post them up please.

Please see my layout attached.

[Phoenix]

Are you able to put up an oscillogram or two showing the phenomenon? And a photo of your circuit including your probe?

Without either of these nobody will be able to help with informed ideas. Lots of things cause apparent gate ring, some real some not. And you help can understand the cause by understanding when during the switching event it occurs.

[stretchyman]

Oh, forgot to mention, you can not use a long earth lead on the 'scope and must use a grounding spring around the probe. This is actually what your 'Problem' actually is as that's what I discovered for myself!

Should have mentioned it sooner!

Please as with ANY 'issue/problem' please post up clear pictures and details as would help somewhat.

We are here to help and have (definitely in my case) seen most common issues before.

50+ years of problems to solve for me so far!

J.

[notadave]

I have taken all of those into consideration. Many measurements have been made with multiple probes, oscilloscopes, ground connections.
I have not given the requested information on purpose as I know the train of thought and have no interest in following it. I have not come here to talk about layout inductance. I have stated that multiple times now.
Multiple engineers have looked at the problem. The layout was done by a seasoned now retired layout engineer with more than 30 years of experience.
The FET I use has the common GDS pin arrangement.
I am aware of one more solution to the problem: Kelvin Source Pin (I have never tried it.)
"The Kelvin pin is an extra pin in addition to the drain, gate, and source in MOSFETs."
Thus the pin arrangement can be KGDS which reduces the package parasitic L and may enable better layout.
That is the only option I know of that treats the cause of the problem.
If there were a way to reduce the di/dt that would help too.

[notadave]

I wrote that I was able to sense a magnetic field close to the package.
That could perhaps be used.
If I had a very lossy ferrite I could attach it to the package front.
or
I could tie a 150 um wire around the package many times.

[stretchyman]

I have not given the requested information on purpose as I know the train of thought and have no interest in following it.

Therefore I and possibly others will help you no further.

J.

[AnalogTodd]

I have taken all of those into consideration. Many measurements have been made with multiple probes, oscilloscopes, ground connections.
I have not given the requested information on purpose as I know the train of thought and have no interest in following it. I have not come here to talk about layout inductance. I have stated that multiple times now.
Multiple engineers have looked at the problem. The layout was done by a seasoned now retired layout engineer with more than 30 years of experience.

Here's a story that may make you re-think your stance:

One evening as I was about to head home from work, I was walking through the lab to go through the back door and leave. My boss was in the lab, staring at a schematic and part, pulling his hair out in frustration. I stopped to ask what was happening and he said he was trying to figure out what was wrong with the part, it had failed high-reliability testing and we hadn't been able to figure out the failure mode. The failures kept us from shipping parts to a BIG customer, and we were now a year delinquent in shipping units.

I sat down and asked what was happening for the failure mode and what measurements had been made as I started reviewing the schematic myself. He told me what was happening, and that people with MANY more years of experience than I had looked at it and been unable to find the failure mode. I asked for a couple voltage measurements when the circuit was active and he made them, pointing out that this was what everyone knew already. Everyone had surmised it was one particular transistor but couldn't say what was wrong.

The next thing I asked was for him to turn off the circuit and measure the resistance from emitter to collector on the device. He just looked at me and said, "It's a transistor, it will read open circuit!" I asked him to humor me. It measured 2k. Now, all the measurements made sense. I was subsequently instructed that we had a major meeting with the customer the next day and I was now to be part of it. While in that meeting the next morning, we had a copy of the layout for that part of the chip that we stared at as management started the talks with the customer. Looking at it, I asked my boss about spacing for one mask versus another and was quietly told to go find out immediately before we had to talk.

It turned out the spacing had been done wrong and we were blowing an oxide with excessive voltage. The next day our FA department found the exact failure location on a part. We worked to get fixes done and kept the customer in the loop and within a few months had resumed shipments.

The moral of the story is to not assume you or anyone else "knows" that a direction someone is asking you to go is wrong. What had been failing for a year and stared at by multiple engineers that were decades my senior was something that a junior engineer with a fresh pair of eyes and no preconceived notions found in less than 24 hours and had it verified within 48 hours.

So yeah, go ahead and refuse the help.

[ftg]

...
Multiple engineers have looked at the problem. The layout was done by a seasoned now retired layout engineer with more than 30 years of experience.
...

Wouldn't this mean that they were more used to slower transistors and lower switching frequencies?
I have received compromised RF layouts from people who had decades more layout experience than I did.
Mostly because they had not done much of RF at all before.

[DavidAlfa]

No schematic, no layout... let us take the glass ball and guess what could be wrong...

[notadave]

when during the switching event it occurs.

One of the FETs starts going conductive then the other FET's diode closes. That kicks off the transition and the oscillation.

The reverse recovery causes a huge di/dt and thus a negative voltage spike over the LS.
That voltage is part of UGS causing the gate to measure a huge negative voltage, that is not over the gate isolation.
The spike does disturb the gate driver to gate loop.

The oscillation seizes once the output phase has transitioned. The time is long enough for roughly 10 periods.
I can provide screen shots next week. The frequency varies between bridges. I can't say if it is the position on the PCB or the devices.

[notadave]

Wouldn't this mean that they were more used to slower transistors and lower switching frequencies?
I have received compromised RF layouts from people who had decades more layout experience than I did.
Mostly because they had not done much of RF at all before.

Yes, that happens, but I am an RF engineer and the engineer in question had done power too, not just digital (Which trains the wrong intuitions/habits).
Other engineers that looked had experience in power and 400V DC high power.
We all know the difference between a loop with low area and a loop with large area. We triple checked. There are no dumb mistakes in the design.