The art of logic signal manipulation with analogue components (D/R/C)

[max.wwwang]

[Original title:  Please help figure out what's going on here]

Can someone experienced in digital circuits please help me understand what the tricks here are. It's part of a digital circuit; its interaction with the world outside it is all digital (LOWs and HIGHs). This is fine. But in this little part, I find it very difficult to understand the function of the resistors and diodes in the areas [1] and [2].

This is drawn up by myself based on a circuit board of my repair project, which I carefully checked many times so it should be correct. Simply because I don't understand what's going on here, chances are the components are arranged in a very bad way which might otherwise be much more revealing and intuitive!

[Edit] Have added a tidier (I think) version. Both are the same thing.

[Psi]

Well R80 and D7 will increase the pull to ground (extra to what R81 does) if  the right side of the capacitor goes negative.
So it seems to be protection so changing states on the capacitor C22 cannot try to pull the input of U9C below ground and damage it.
Seems kind of unlikely through with 220k in series but maybe it's just there to stop the cap charging up negative because that causes some other problem, like a slower response when it changes to high.

D5 appears to be changing how much current feeds into the RN7C filter network when the input voltage is above 0.7V.
Might be to prevent a LOW signal from discharging C20 since it will have to discharge through the 220K. But a HIGH can go through the diode (less 0.7V and charge C20 quicker.

Just guessing though, I dunno exactly what that thing does

[max.wwwang]

Well R80 and D7 will increase the pull to ground (extra to what R81 does) if  the right side of the capacitor goes negative.
So it seems to be protection so changing states on the capacitor C22 cannot try to pull the input of U9C below ground and damage it.
Seems kind of unlikely through with 220k in series but maybe it's just there to stop the cap charging up negative because that causes some other problem, like a slower response when it changes to high.

It is also what I thought is possibly the only use of D7. But as you said, can this be possible (and it requires the negative voltage to be less than -0.6V or so for D7 to be useful)? Possibly yes ...

D5 appears to be changing how much current feeds into the RN7C filter network when the input voltage is above 0.7V.
Might be to prevent a LOW signal from discharging C20 since it will have to discharge through the 220K. But a HIGH can go through the diode (less 0.7V and charge C20 quicker.

Just guessing though, I dunno exactly what that thing does

Find it hard to get my head around here.

At first I think we can ignore C20 and C21 since they appear to be just 'standard' capacitors that exist everywhere near any chip (I understand they are for noise filtering, for example). It's just C22 that seems a real deal because it's in serial with the line, not bypassing. But physically they three are all the same puppy (same look, same physical size), though I'm not sure if they have the identical capacitance.

[wasedadoc]

The resistors and diodes around C20 and C22 are delay networks. Low to high transitions are delayed less than high to low. C22 with resistors and diode form a short pulse when the preceding U11B changes state. The input to U9C will return to low even if the output of U11B remains high.

[max.wwwang]

The resistors and diodes around C20 and C22 are delay networks. Low to high transitions are delayed less than high to low. C22 with resistors and diode form a short pulse when the preceding inverter changes state.

That's very specific and interesting! I may possibly set up a minimal circuit to demonstrate this. (Or perhaps the easiest way is simply to probe these pins!)

For the second bit, I presume it applies only on one side of the pulse on the output pin of U11B? Is it like an overshoot on the falling edge?

Anyway, I'm convinced that these passive components are essentially all for the tweaking of the signal, be it delay, push, sharpen, strengthen, dampen, or whatever.

[pcprogrammer]

The way I see it is that the whole circuit is set up to be edge sensitive. It depends on the rest of the circuit as to why they did it this way.

If you have the board this is on, in a working state, then sure you could probe it to see what is happening.

The RC filters in the first section cause a delay between one input of the NAND or NOR gates connected to the input signal. This can be used to create pulsed signals. The so called differentiator or high pass filter in the second stage does this to. On a low to high change on the output of U11B the signal after the capacitor will go high and then slowly decay to low again, based on the RC time given by C22 and R81. When the output of U11B changes from high to low the signal after the capacitor goes below ground level and will then increase more rapidly based on the RC time given by C22 and the combination of the series resistance of R80 and D7 parallel to R81.

The diodes in the first section bring different delays for low to high and high to low signal changes.

[max.wwwang]

The way I see it is that the whole circuit is set up to be edge sensitive. It depends on the rest of the circuit as to why they did it this way.

If you have the board this is on, in a working state, then sure you could probe it to see what is happening.

The RC filters in the first section cause a delay between one input of the NAND or NOR gates connected to the input signal. This can be used to create pulsed signals. The so called differentiator or high pass filter in the second stage does this to. On a low to high change on the output of U11B the signal after the capacitor will go high and then slowly decay to low again, based on the RC time given by C22 and R81. When the output of U11B changes from high to low the signal after the capacitor goes below ground level and will then increase more rapidly based on the RC time given by C22 and the combination of the series resistance of R80 and D7 parallel to R81.

The diodes in the first section bring different delays for low to high and high to low signal changes.

Thanks. That's very helpful.

Yes, I have the board with this part of circuit, which is a part of my repair project. And true, its working almost entirely relies on the pulses, either falling or rising, and their timing and synchronisation, etc. I hope this part is working so I can probe around and have a visual appreciation of the function of these parts (if not working, I'm striving to bring it back up and running).

Are you able to comment on the function of R78 on the top, tieing up the output and input pins of two gates in one continuous signal path? I came across this and had this question before. Thanks.

[pcprogrammer]

I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.

[max.wwwang]

I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.

Yes, positive feedback, as it appears!

What still baffles me is that, these are not analogue components (such as op-amps, where feedback is common) but logic ones. They don't quite care too much about the slight difference in voltage as long as they are well above or below the threshold differentiating HIGH and LOW.

[wasedadoc]

I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.

The primary function of R78 is not to alter C21 charge or discharge rate.

The positive feedback provided by R78 gives a Schmitt trigger characteristic to the U9E inverter.  The RC delay components convert the step waveform at the N1-3D-4 input to an exponential one, ie a relatively slowly rising or falling waveform.  If R78 were not present, at some point this waveform would cross the threshold of the inverter input and cause its output to toggle.  However the slowly changing input makes it sensitive to noise so the inverter output might not be a single transition but instead a few fast toggles before reaching steady state.  With R78 providing a small amount of positive feedback the exponential waveform receives a small addition if rising (and subtraction if falling) so that once the threshold is crossed the inverter output toggles cleanly just once.

[TimFox]

D5 shortens the delay for positive-going input, compared to the long delay through all the resistors for negative-going input.

[max.wwwang]

Thanks wasedadoc and TimFox. I've added a tidier version above.

That all makes good sense. If I understand correctly, these R/D/C components only either slightly modify the signal or help the gates work more 'cleanly', but do not change the HIGHs or LOWs of the signal by, say, turning things up side down.

If this is the case, looking at the upper half, it appears to me the output on N1-4D-11 will always be LOW regardless of the input signal on N1-3D-4, because the two inputs to U18D will always be one HIGH the other LOW. Then what's the point here?

It is possible that, due to the delays such as by softening the rising or falling of the signal, i.e. the change of the timing of the rises and falls (with reference to the HIGH/LOW threshold), there might also be HIGH outputs on N1-4D-11 (i.e. a square wave signal). If this is correct, then the values of these R/D/C components would have required a careful calculation and tuning by the designer. This is not unlikely because of the existence of the pod (R73), which allows adjustments by end user.

For the lower half, what will be the initial status of U11B pin 5 be if I want to mentally 'simulate' its working (suppose its pin 6 is HIGH)?
[Edit] This is not a question --- it should be LOW at the beginning because of its connection to GND.

I will see if I can confirm these on a scope if this part of the circuit is working.

[max.wwwang]

The right half of the lower part, consisting of U9C, U9D, and U11B, appears to be essentially an inverter, probably with some tricky tweaking (of timing) of the input signal.

[wasedadoc]

If this is the case, looking at the upper half, it appears to me the output on N1-4D-11 will always be LOW regardless of the input signal on N1-3D-4, because the two inputs to U18D will always be one HIGH the other LOW.

You should learn to draw timing diagrams. Your conclusion about the output of U81D is incorrect.

Start with the input N1-3D-4 being HIGH and the inverter output LOW. The NOR output will be LOW. Now make N1-3D-4 go LOW. The direct input to the NOR gate goes LOW imediately. But its other input remains LOW for some time because of the RC delay to the inverter input.  So there is a period when both of the NOR inputs are LOW which makes its output HIGH. The variable resistor allows adjustment of that pulse width.

[max.wwwang]

Start with the input N1-3D-4 being HIGH and the inverter output LOW. The NOR output will be LOW. Now make N1-3D-4 go LOW. The direct input to the NOR gate goes LOW imediately. But its other input remains LOW for some time because of the RC delay to the inverter input.  So there is a period when both of the NOR inputs are LOW which makes its output HIGH. The variable resistor allows adjustment of that pulse width.

Yes, I get that. Thanks.

[wasedadoc]

When the N1-3D-4 input goes HIGH again the diode lets the capacitor charge up at a much faster rate than it discharged so the circuit returns to the initial state of my preceding post quite quickly to be ready for the next HIGH to LOW transition of the N1-3D-4 input.

[max.wwwang]

In another similar, but simpler, case (RHS of the circuit), I think the output on N2-6B-4 and N2-6B-11, based on the ON/OFF status of the transistor, will be like, roughly, as shown in the timing diagram.

[Edit] Capacitors are not specified. I'm assuming they are identical.

[pcprogrammer]

Ha, another failure of the image system. When I click on the timing diagram I get another image. 



But yes the exclusive or gate 2-6B-C will detect the state of the transistor.

Code: [Select]

XOR
0 0 ==> 0
0 1 ==> 1
1 0 ==> 1
0 0 ==> 0

But again there is some pulse forming done with the other gates and the RC filters. Which seem to be in your timing diagram, but hard to see if it lines up without the big version of it.

Edit: Found the relating image in another thread. (here)

[max.wwwang]

Thanks.

I was aware of the XOR operation, and used it in deriving the diagram.

It's not clear to me in your response. Do you think my diagram is largely correct?

By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?

[pcprogrammer]

I'm still looking at the signals 

The RC setup here constitutes a low pass filter. Only the -3dB point is fairly low. So to me, but also not an expert, it is a filter.

Edit: The timing diagram looks ok, but it might be that the timings on the inputs 2-6B-1 and 2-6B-2 are the other way round. This depends on the values of the two capacitors. But assuming they are the same the delay on 2-6B-1 will be longer due to R32 being 10K, and R34 only 2K2. The actual times can be calculated but the value of the cap needs to be known.

[max.wwwang]

You are right. I took it as 2k2 > 10k in making the diagram. 

Yes, 2-2B-1 and 2 should be the other way round in terms of the amount of delay. Thanks.

So my guess here is that the two outputs are one normal H the other normal L (which may be taken as L active or H active, respectively, for their downstream users), but both will send a pulse (the width probably does not matter) when a change of state of the transistor is detected (from ON to OFF or the other way round). And there is a timing difference between these two pulses.

Why it is so will need more investigation. Thanks!

[wasedadoc]

By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?

Correct.  Both R32&C and R34&C are to make delays, not to act as filters.

[max.wwwang]

I've added the correct version of the timing diagram. Note --- for illustration purpose, it's only the order of events that matters, not the actual pulse width. See picture "sync".

For simplicity, in this case, it's assumed that the input pulse width is always wide enough for the delayed signals to transit.

To add a bit fun, I've looked into what it looks like if without such condition, i.e. if the input pulse width may not be wide enough for the delayed signal to flip. This is in diagram "sync-1".

These timing diagrams are all created 'programmatically' with Excel. Arbitrary input signal is created with random number generator. Timing diagrams are drawn automatically with conditional format. For those interested, I've also attached the Excel spreadsheet for this. There is no guarantee it will work as intended on your machine (this is far from uncommon for M$ products).

On my machine, pressing Shift-Alt-Ctrl F9 will cause the spreadsheet to 'recalculate' and change randomly the input signal and, of course, the output signals.

[Edit] A bug in the formulas fixed. Diagrams updated.
[More edit] The Excel file has been taken off due to an obvious lack of interest, or abundance of caution (which is good), or both.

[max.wwwang]

Now how the D/R/C components work in between the gates in the circuits of the original post is crystal clear to me. I also now understand how R78 (in the original post) works as feedback (just like feedback of op-amps), though haven't yet got into the very detail. When you know, it's so simple. Good learning!  Thanks to the experts! 

Timing diagrams for those can also easily be made. Will do when time allows, or when my repair (reverse engineering) project comes to that point.

[pcprogrammer]

By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?

Correct.  Both R32&C and R34&C are to make delays, not to act as filters.

To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.

Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.

Added an image plucked from the net to show this filtering.

[wasedadoc]

By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?

Correct.  Both R32&C and R34&C are to make delays, not to act as filters.

To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.

Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.

Added an image plucked from the net to show this filtering.

1.  We don't know the value of the Cs but I'd wager the gate delay contributes very much less delay than the RC.

2.  Yes, RC forms a low pass filter but that is not the aim here.  The values of R and C were not computed  to give some specified value of attenuation at some specified frequency.  Rather they were computed so that the exponentially rising or decaying waveform reaches approximately 50% after some required time.   

[pcprogrammer]

1.  We don't know the value of the Cs but I'd wager the gate delay contributes very much less delay than the RC.

Correct, and that is also not what I intended to state. The gate is needed to reshape the signal edge and in combination with the other input to make the pulse. The delay of the gate itself will indeed be negligible.

2.  Yes, RC forms a low pass filter but that is not the aim here.  The values of R and C were not computed  to give some specified value of attenuation at some specified frequency.  Rather they were computed so that the exponentially rising or decaying waveform reaches approximately 50% after some required time.

I agree that the designers made calculations based on the RC time and were not aiming for a specific -3dB point.

Looking at a datasheet for a CD4030 when powered from 10V Vin low is max 3V and Vin high is min 7V, so depending on the actual supply voltage and the Vout of the first gate the times can be calculated. But for this the value of the capacitor needs to be known. I would have to search for the formula to do so. I do remember that t = R * C, and that after ~5t the capacitor is at near the supplied voltage.

Since max.wwwang indicated his intention to learn, it helps to provide as much information as is helpful. 

[max.wwwang]

To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.

Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.

Added an image plucked from the net to show this filtering.

In some sense that's correct. And that's exactly what's illustrated in my second diagram (sync-1) with narrow pulses of the input signal, which means nothing but higher frequencies! In that case, i.e., when the frequency of the input signal is high enough, it will be essentially blocked (more precisely, bypassed) by the R/C 'filter', so some transitions of the input signal will be invisible to what connects to the output pins (and the output signals become less comprehensible --- at least to me). After all, and obviously, the R/C components don't know, and don't care, what hat we are putting on their heads! They just do what they are supposed to do. 

But in this case, I would say --- practically --- because the input signal is driven by mechanical parts, its frequency is unlikely to be very high (i.e., the speed of the machine is unlikely to be too high at one moment then all of a sudden too low, or the other way around). Practically, the R/C  bit is working more to introduce delays to create corresponding pulses, reflecting specific transitions in the input signal, feeding downstream of the circuit.

All good points and good debate, by the way!

[wasedadoc]

Looking at a datasheet for a CD4030 when powered from 10V Vin low is max 3V and Vin high is min 7V, so depending on the actual supply voltage and the Vout of the first gate the times can be calculated. But for this the value of the capacitor needs to be known. I would have to search for the formula to do so. I do remember that t = R * C, and that after ~5t the capacitor is at near the supplied voltage.

Those 3 and 7 Volt numbers are what TI give as spec limits below and above which the input will certainly be treated as a LOW or HIGH respectively when powered at 10 volts.  In practice the LOW to HIGH and HIGH to LOW transition voltages will be much closer to each other than those numbers suggest.  They will be slightly different between individual ICs and may also vary slightly with temperature.  I have not done an analysis but would not be surprised if the range of actual delay times encountered differed by as much as 20% of the calculated value.

[pcprogrammer]

I have not done an analysis but would not be surprised if the range of actual delay times encountered differed by as much as 20% of the calculated value.

No surprise there when you take component tolerances into account. The resistors will most likely be standard 5% ones and the capacitors used are most likely to have 20% tolerance.

In this part of the circuit it probably did not matter that much, but in the one given in the original post the potentiometers are there for a reason and it might well be to adjust for these tolerances.

Here a bit more about the filters to make the delay. Think Fourier and how a square wave is made up from an infinite set of sine waves with different frequencies and amplitudes. The RC combination filters the sine waves with frequencies above the -3dB point.

[max.wwwang]

I thought I got what's going on here, but probably not (at least not fully).

I would like a bit more discussion about the feedback of the upper half of the circuit through R78 (later maybe more in-depth analysis of the other parts of the circuit).

Assumptions:
Input signal frequencies are NOT so high to make the RC work like a filter, i.e. no bypass of any of the input pulses.

Symbols:
d1: delay on the rising edge of the input by D/R/C
d2: delay on the falling edge of the input (d2 >d1)

I've laid out the characteristic stages of the input signal and the levels (or trends) at points of interest, so we can figure out the current flowing through R78 at each of these stages. The feedback is considered "positive" when there is a current flowing backwards (from right to left), and vice versa. All in the diagram.

What exactly is the purpose of the feedback here?

I guess the most significant moments here are probably when crossing the threshold voltage, as highlighted in green.

Overall, apart from the nuances that R78 might bring into the equation, the function of this circuit is to detect the falling edge of the input and issue a constant width (that of the longer delay) pulse every time when the input signal falls to low.

(Also included is, again, another 'simulated' - by Excel - output of a random input.)

[Edit]

I think now I've figured out, indeed it's like a Schmitt trigger characteristic to reduce the bouncing between L/H when crossing the threshold. But this is only for the falling edge, which is more necessary because it's less steep. Will double check and update with more analysis ...

[max.wwwang]

Here a bit more about the filters to make the delay. Think Fourier and how a square wave is made up from an infinite set of sine waves with different frequencies and amplitudes.

This is no doubt correct.

The RC combination filters the sine waves with frequencies above the -3dB point.

The textbook doctrine may not apply here. In this case, or cases similar to this, the frequencies it blocks (or not) depend on the threshold voltage of the gate.

[pcprogrammer]

The RC combination filters the sine waves with frequencies above the -3dB point.

The textbook doctrine may not apply here. In this case, or cases similar to this, the frequencies it blocks (or not) depend on the threshold voltage of the gate.

The gate threshold voltage has nothing to do with the sine wave frequencies being blocked. The threshold voltage in combination with the RC time are what make up the delay the circuit is designed for.

Mark that I mention sine wave and not square wave. I know it is semantics, but what I'm trying to get across is that any RC combination is a filter, no matter the intent of the circuit. Sure it can be used to make a delayed signal, which is done in this case.

I would like a bit more discussion about the feedback of the upper half of the circuit through R78 (later maybe more in-depth analysis of the other parts of the circuit).

.......

I think now I've figured out, indeed it's like a Schmitt trigger characteristic to reduce the bouncing between L/H when crossing the threshold. But this is only for the falling edge, which is more necessary because it's less steep. Will double check and update with more analysis ...

The circuit with R78 can be seen as a network with two supplies (or sinks) and as such you can do calculations on it.

But a simple view is that when the output of the gate goes high it will slightly raise the voltage at the input and with that make sure that it stays above the threshold until the other supply (essentially the voltage across the capacitor) lowers so much that it falls below the threshold and the output of the gate will then also go low, and with doing this it will drop the voltage at the input below the threshold to make sure it stays below the threshold. It might be that they needed it to suppress some noise and adding this resistor made it stable.

Just like a Schmitt trigger circuit, as you already found out yourself.

[wasedadoc]

1. Thinking in terms of sine waves and their frequencies is not helpful when analysing these RC plus gate delays.  Instead consider the time domain. Start with zero voltage on the capacitor and then apply a voltage step to the input R.  Any decent textbook on circuit analysis will show the derivation of the formula for the voltage on the capacitor after a time t.

Vout = Vin(1-exp(-t/RC))

Where Vin is the height of the step and exp() means e (that 2.718 ... number) raised to the power of the number in the ().

Using that formula it is possible from R and C to compute the time to reach a target voltage or conversely to compute the RC product to reach a target voltage after a desired delay.  For example if the target voltage is 50% of the step height then

Vout/Vin = 0.5 = 1-exp(-t/RC)
exp(-t/RC) = 0.5
take natural logarithm of each side
-t/RC = -0.693
RC=t/0.693 or t = 0.693RC

The same analysis holds if we start with the voltage having been applied for a sufficiently long time that the capacitor has been fully charged and then it is changed to zero so that the capacitor discharges through the resistor.  Vout = Vin(exp(-t/RC))

2.  Despite sine waves and their frequencies not being used in the above, the inverse of frequency, that is period, does need to be considered if the input is not a single step but a sequence of pulses.  Clearly if the input LOW and HIGH times are too short then the capacitor does not reach the starting conditions assumed above.

3.  The 20% figure I wrote above was not because of the tolerances on the R and C.  It was the uncertainty of the logic gate's threshold voltage.  The spec says that worst case it can be anywhere between 3 and 7 volts when powered at 10 volts.  It is more likely to be nearer the middle of that range than the extremes but it will not be exactly the same for every individual chip, even if the same type number from the same manufacturer.

[feedback.loop]

Please next time try to make the subject line more specific.
Thank you.

[max.wwwang]

Please next time try to make the subject line more specific.
Thank you.

Feedback taken. 

[wasedadoc]

Re the changed title in the topic list.  In a sense there are no digital signals.  All practical signals have analogue characteristics but may be conveying digital information.  Considering their analogue requirements becomes increasingly important as the bit rate increases.

[max.wwwang]

Double checked and can confirm what I said earlier as correct. Tried to derive the formulas but found my math is a bit rusty  ,  so will need to refresh my calculus with a textbook before I'm able to do that  (but I will do it!). Notwithstanding this, qualitative analysis suffices here.

Have included the equivalent circuits at the start of several significant periods. Simplification has been made to make it clearer: when the diode is on, the resistors in parallel are ignored due to their significantly greater resistance than 10k (assuming the pot is also a big one). Have also included the revised timing diagram.

I said that the moments when the threshold voltage is crossed are significant. That's correct. But the second transition is more so, because of --- instinct tells me --- the change of direction of the feedback current before and after the crossing. That moment is now highlighted in orange to indicate its greater significance.

(You will need to excuse the messy and inconsistent component numbering because this is automatic and out of my control.)

[max.wwwang]

The gate threshold voltage has nothing to do with the sine wave frequencies being blocked. The threshold voltage in combination with the RC time are what make up the delay the circuit is designed for.

Mark that I mention sine wave and not square wave. I know it is semantics, but what I'm trying to get across is that any RC combination is a filter, no matter the intent of the circuit. Sure it can be used to make a delayed signal, which is done in this case.

We are talking about different things when both referring to "frequency". You are talking about the invisible sine waves making up the square wave. I'm talking about the visible and apparent square waves. If sine waves, or bypassing or blocking thereof, of course it has nothing to do with the gate characteristics.

The circuit with R78 can be seen as a network with two supplies (or sinks) and as such you can do calculations on it.

But a simple view is that when the output of the gate goes high it will slightly raise the voltage at the input and with that make sure that it stays above the threshold until the other supply (essentially the voltage across the capacitor) lowers so much that it falls below the threshold and the output of the gate will then also go low, and with doing this it will drop the voltage at the input below the threshold to make sure it stays below the threshold. It might be that they needed it to suppress some noise and adding this resistor made it stable.

Just like a Schmitt trigger circuit, as you already found out yourself.

Emm, yes. Everyone will have their own best way of intuitively, or theoretically, understanding what is exactly going on here.

I just find it not very helpful to stop with merely saying the feedback either raises or lowers the input, as the case may be, as if some magical parcels are being sent by a magician as we wish. I need something more concrete than that.

[max.wwwang]

1. Thinking in terms of sine waves and their frequencies is not helpful when analysing these RC plus gate delays.  Instead consider the time domain. Start with zero voltage on the capacitor and then apply a voltage step to the input R.  Any decent textbook on circuit analysis will show the derivation of the formula for the voltage on the capacitor after a time t.

Vout = Vin(1-exp(-t/RC))

Where Vin is the height of the step and exp() means e (that 2.718 ... number) raised to the power of the number in the ().

Using that formula it is possible from R and C to compute the time to reach a target voltage or conversely to compute the RC product to reach a target voltage after a desired delay.  For example if the target voltage is 50% of the step height then

Vout/Vin = 0.5 = 1-exp(-t/RC)
exp(-t/RC) = 0.5
take natural logarithm of each side
-t/RC = -0.693
RC=t/0.693 or t = 0.693RC

The same analysis holds if we start with the voltage having been applied for a sufficiently long time that the capacitor has been fully charged and then it is changed to zero so that the capacitor discharges through the resistor.  Vout = Vin(exp(-t/RC))

Inspired by the formulas, had a crack on this case. With simplifications as illustrated, I've got the formula for voltage across C over time for stage (2). From here, it's not too difficult to figure out time needed for the capacitor to reach any given voltage (between 0 and V*).

So this is the result of a quantitative analysis.

[Edit] * If we are going to be really precise, Vc will never reach V, but rather always less than V because of the ever-going current through all of the three resistors, hence the voltage drop on the first R1 (LHS of C). To be even more precise, its theoretical maximum (or "limit" in mathematical language) is the voltage at that point of the voltage divider formed by the three resistors, that is V/r (this means "between 0 and V" above should read "between 0 and V/r").

As TimFox rightly pointed out in this thread, C will never be "fully charged" in any finite amount of time, "only approach[ing] an asymptote". (This is so even in the simplest textbook RC charging circuit.)

[pcprogrammer]

And here I think you went wrong. See this thread for info about "Thevenin Equivalent"

The RC time is not based on the 10K resistor, but the resulting resistance of the parallel and series resistors.

That is why I wrote about calculations on networks in the earlier post where I gave a simple view on the positive feedback.

There are several ways to approach such networks. You can use Kirchhoff's laws or use Thevenin's equivalent or Norton's theorem.

[max.wwwang]

And here I think you went wrong. See this thread for info about "Thevenin Equivalent"

The RC time is not based on the 10K resistor, but the resulting resistance of the parallel and series resistors.

That is why I wrote about calculations on networks in the earlier post where I gave a simple view on the positive feedback.

There are several ways to approach such networks. You can use Kirchhoff's laws or use Thevenin's equivalent or Norton's theorem.

That's exactly the same problem.
I'm not sure if my formula is misunderstood. Nonetheless, I've updated its form only to make it clearer.

[pcprogrammer]

Yes, and your adjustment still feels wrong. It has been to long since doing this kind of math, but you are using C * R1, which is not the correct base for doing the calculations.

The numbering of your resistors is wrong for proper formulating this, but since both 10K resistors are named R1 and of the same value I'm using it in both terms.

The RC time in this case is C * ((R1 * (R1' + R2)) / (2R1 + R2))) Due to the fact that R2 is big compared to R1 the difference is not that big. Only ~120 Ohms.

The capacitor will only charge to the Thevenin equivalent voltage, which is calculated by V * ((R1' + R2) / (2R1 + R2)), which is only slightly less then V.

These are the values to use in the calculation for determining the voltage across the capacitor over time.

Edit: to explain, the resistance to use for the RC time is also based on the Thevenin equivalent of them being in parallel, that is R1 is parallel to the series resistance of R1' and R2.

[wasedadoc]

1.  I think we are agreed that the charge and discharge of the capacitor are not symmetrical and it is the longer one (diode path not operating) that is of interest.  In which case it is the discharge curve you should focus on.

As advised by pcprogrammer you ned to calculate the source voltage and resistance equivalent to the resistors you have and the voltages applied to them.  When the HIGH to LOW threshold is reached and the gate changes state the equivalent circuit will change and so will the discharge curve.  It will be slightly faster but that is not really of any consequence if it is only the delay to the switching time that you are working out.

2.  It is true that in theory the capacitor never becomes fully charged or discharged.  However the discrepancy from the asymptotic value becomes small.  Below is the percentage discrepancy for some values of t= nRC:

n=1:  36.8%
n=2:  13.5%
n=3:  4.98%
n=4:  1.83%
n=5:  0.67%
n=6:  0.25%

[max.wwwang]

Yes, and your adjustment still feels wrong.

Thanks for your use of "feel" now. You are entitled to have your feelings, whatever they might be! 
Just to be absolutely clear, I'm not saying 100% absolutely the formula I reached is correct. I can be wrong! 

It has been to long since doing this kind of math, ...

That's all good. Same here. Most of us are probably not mathematicians I would guess.

..., but you are using C * R1, which is not the correct base for doing the calculations.

Don't quite get this, since there is an "r" in the equation.

The numbering of your resistors is wrong for proper formulating this, but since both 10K resistors are named R1 and of the same value I'm using it in both terms.

I'm OK with that. Here R1/R2 are not meant to be numbering, but rather variables for the resistance to make it (a little bit) more generic. Since the two resistors have the same value, they are represented by R1, which is OK to me. This even does not lose the generality for the cases when the R's at the LHS and RHS of C are different.

What I have done is simply 1) a specific definition of the problem, based on reasonable simplification from the real world one, and 2) tackle that defined problem with mathematical methods and electronic rules. Simple as that. There is no intention to be perfect or cover cases beyond what has been specified.

The RC time in this case is C * ((R1 * (R1' + R2)) / (2R1 + R2))) Due to the fact that R2 is big compared to R1 the difference is not that big. Only ~120 Ohms.

The capacitor will only charge to the Thevenin equivalent voltage, which is calculated by V * ((R1' + R2) / (2R1 + R2)), which is only slightly less then V.

Don't completely get this. But I didn't say that the final Vc will be less than V, at a greater magnitude than it should be (according to the formula and the values of the components).

These are the values to use in the calculation for determining the voltage across the capacitor over time.

Edit: to explain, the resistance to use for the RC time is also based on the Thevenin equivalent of them being in parallel, that is R1 is parallel to the series resistance of R1' and R2.

Elaboration or, even better, step-by-step derivation would be great. But, of course, no obligations!

Only one point, I get the point of resistors in parallel. But note that it's only one 'branch' of the parallel that's charging the C.

[max.wwwang]

1.  I think we are agreed that the charge and discharge of the capacitor are not symmetrical and it is the longer one (diode path not operating) that is of interest.  In which case it is the discharge curve you should focus on.

Correct, that has been agreed on. But the charging stage happens to have been chosen for a quantitative analysis. This is not to say this stage (as the subject of the quantitative analysis) is more significant. It's not too long a way, from here, to a similar formula (or formulas) for that (more significant) stage, if need be.

As advised by pcprogrammer you ned to calculate the source voltage and resistance equivalent to the resistors you have and the voltages applied to them. ...

Dont' quite get this. What I did is based on first electronic principles (that is from scratch). I don't understand, in that approach, why I need to calculate anything like "equivalence".

...  When the HIGH to LOW threshold is reached and the gate changes state the equivalent circuit will change and so will the discharge curve.  It will be slightly faster but that is not really of any consequence if it is only the delay to the switching time that you are working out.

This is true for that stage, but not for this (stage 2) as the subject of the current analysis. There is no dispute about that from me (with regard to that stage).

2.  It is true that in theory the capacitor never becomes fully charged or discharged.  However the discrepancy from the asymptotic value becomes small.

Good to hear that. We are in agreement. By the way, I didn't say anything that can be read as the discrepancy will not become small. 

Below is the percentage discrepancy for some values of t= nRC:

n=1:  36.8%
n=2:  13.5%
n=3:  4.98%
n=4:  1.83%
n=5:  0.67%
n=6:  0.25%

I have not done the math here. But I presume you are referring to the basic textbook RC charging circuit here? In that case, not a problem!

However, correct me if it's not the case and please elaborate. 

[pcprogrammer]

To gain some insight in why the equivalent voltage and resistance just take a look at this video.



Or read this explanation about it.

Also a google (or other search engine) search can shed a lot of light. Gives for instance the wiki page about Thevenin.

Look into "solving electrical networks" for other theories and laws. I mentioned some of the big names before.

By the way the video and the article where mentioned in the thread I pointed to earlier.

[max.wwwang]

To gain some insight in why the equivalent voltage and resistance just take a look at this video.
...

Thanks again. But can I ask you --- have you realised my formula is exactly what's been given in the video? (Just put "R1+R2" into "R2" of the equation of the video). For convenience, I've attached a snapshot of that equation as well as the associated circuit.

By the way, I was well aware of these methods (though I used a harder one than this --- I used the differential equation approach but gosh I got the same result  ).

[Edit: Just to be honest and straight --- although I did know these methods, I don't recall using them in problems like this before. But my memory often fails me, I know!]

But thanks for these resources anyway! 

This is useful because now I'm reasonably sure that my formula was correct! 

[max.wwwang]

I think the upper half of the circuit in the OP has been resolved satisfactorily without dispute (hopefully). I'm now looking closely into the lower half (attached here again for convenience --- but excuse me for the change in numbering).

The LHS of it (in the red dash line box) is very simple now, so does not need more attention. The RHS (in the blue dash line box) looks similar but is different because C is serial in line, not wired like a bypass capacitor.

I've included a manual simulation of it, along with the LHS, to show what the who thing does between the input N1-3D-4 and the output N1-4C-8. Being normal low, it gives a constant width pulse (determined by C20 and R70) for the falling edges of the input.

(Again, one assumption here is that the input pulse widths are big enough to accommodate the delays of RC both ways, rising or falling.)

As we know, when C20 is charged, then when its LHS suddenly falls to L, its RHS will immediately fall to -V (V as the voltage for H, -11V here). Although for this scenario the discharge of C will be fairly quick (because D is ON so the RC constant is small), pin 9 of U9C will momentarily 'see' a negative input voltage -V (assuming its input impedance is high). If ignoring its input voltage limit, this negative voltage will be interpreted as L.

But there is a range of voltage that the input must not go beyond. This is in the "absolute maximum ratings" of the Toshiba TC4069BP chip. Its input range goes down only to Vss-0.5, which is 0.5V [Edit: -0.5V]. (Snippet of datasheet included.)

The question then is, why is the circuit designed this way without fearing that this negative input voltage (beyond the absolute maximum rating) may damage the chip?

I have carefully checked the PCB and am sure the circuit shown correctly reflects the board.

[wasedadoc]

See the schematic https://www.alldatasheet.com/datasheet-pdf/pdf/50860/FAIRCHILD/CD4069.html


The input has protection diodes and there is that external series 220k resistor. The FETs experiences only small voltages beyond the rails and the currents in the diodes are acceptably low.

[max.wwwang]

See the schematic https://www.alldatasheet.com/datasheet-pdf/pdf/50860/FAIRCHILD/CD4069.html


The input has protection diodes and there is that external series 220k resistor. The FETs experiences only small voltages beyond the rails and the currents in the diodes are acceptably low.

Appreciate your input as always.

Yes, its input may be protected, just like the one you are referring to (Fairchild). And I do know there is a 220k resistance. But if its input impedance is high enough (this is a reasonable expectation because the input current is very low), the 220k resistor will not make any difference in 'shielding' the gate from too low input voltage.

The problem is, this -0.5V is absolute maximum rating, not just a recommendation. And absolute is absolute (included is the Fairchild version; the same thing: -0.5V).

Perhaps I should read "absolute" in a different way?

[pcprogrammer]

It is not about the normal input impedance in this case. The protection diode has a very low impedance for negative voltages, but won't be able to sink a lot of current. Providing a negative voltage from a source with low impedance will allow to much current and this will kill the input protection diode and worst case the whole chip.

The 220K resistor gives an assurance the current won't be too high. Another limiting factor in this circuit is the 10K resistor with the diode in series, which will speed up the discharge rate of the negative pulse.

Also the datasheet states:

Note  1:  “Absolute  Maximum  Ratings”  are  those  values  beyond  which  the safety  of  the  device  cannot  be  guaranteed.  They  are  not  meant  to  imply that  the  devices  should  be  operated  at  these  limits.  The  table  of  “Recommended Operating Conditions” and Electrical Characteristics table provide conditions for actual device operation.

The safety cannot be guaranteed, but it does not mean that it will instantly die when these conditions are met.

[wasedadoc]

The gate input also an internal resistor before the diodes though that is likely to be relatively low value (for speed reason) compared to the external 220k.

If you have a 'scope look at that pin and see what negative voltages that pin experiences.

[max.wwwang]

Ah my assumption is only half correct. If the input voltage is positive, the input impedance is indeed high because of the MOS. However when the input is negative, there will be current through the highlighted path. In this case, although the voltage at the other side of the 220k resistor will be momentarily be as low as -11V, because of this current, the voltage on the input pin of the gate will be much higher than -11V.

I'm not interested in why the gate is not broken -- because of the variation of the specs, one component may well survive an input voltage that goes beyond the recommended or even absolute limits. What I'm interested is, I don't think the designer of this circuit will let it be exposed to an input voltage under normal working condition that goes beyond its absolute maximum based on wishful thinking "I think she'll be alright".

The remaining problem is -- with a correction of my previous assumption --- when the far side of the 220k resistor sees a -11V signal, the voltage on the input pin of the gate may still be higher than the absolute maximum -0.5m (because of the forward bias voltage of the protection diode, and the voltage drop over the internal resistor). This might be narrowly avoided if the voltage drop of the diode is 0.5V (I think there are some diodes the forward bias voltage drop of which is less than 0.6V) or even less than 0.5V, and the internal resistor is so small that its voltage drop is negligible (that's very likely).

[wasedadoc]

11 volts and 220k is only 50uA. Don't need much forward voltage on a silicon diode to conduct that.

[pcprogrammer]

Ever heard of schottky diodes?

These have lower forward voltages than a normal silicon diode. Germanium diodes also have lower forward voltages. (~0.3V)

[wasedadoc]

They are not drawn as Schottky diodes.

It isn't the voltage per se that would cause damage. The FET gates are not susceptible to modest excursions beyond the power rails. It is excessive current through the diodes that could damage them. The spec is saying that up to -0.5 volts at input will be low enough current. The equipment designer has used the external resistor to limit the current.

[pcprogrammer]

They are not drawn as Schottky diodes.

I know. Was not suggesting that these are used in this IC, but merely providing information about there being diodes with lower forward voltages in a response to the below.

(I think there are some diodes the forward bias voltage drop of which is less than 0.6V)

[max.wwwang]

11 volts and 220k is only 50uA. Don't need much forward voltage on a silicon diode to conduct that.

That makes sense.

[max.wwwang]

Yet another example.

From what I can see, the RHS of the circuit normally remains H, but will give a constant width pulse to L on the rising edge of the LHS (but not for falling edges). The problem is, on the falling edge of the LHS, the input pins of U29A will see a negative input as low as -11V, far below the absolute maximum of TC4071BP (which is, again, -0.5V). In this case, there is no buffering resistor between the capacitor and the input pins.

Again, my assumption is that the designer of the circuit should know with certainty that the voltage on the input pins of U29A will not go beyond the absolute maximum rating under normal working condition.

[pcprogrammer]

Did you measure it with a scope?

The input diode will still try to keep the voltage within limits. You can dive into the amount of charge that can flow through the diode in the short time it takes to discharge. It is the amount of energy stored in the capacitor. If the capacitor is small enough it won't harm the chip.

I myself would have added an external schottky diode to makes sure the input is protected.

[max.wwwang]

No I didn't. It's not in a condition that it can run the way it should. I've ordered faulty part and am waiting for it to arrive and hopefully it'll then be fixed, so I can probe all these things and verify all the analyses and theories.

I agree that probably there are also protection diodes inside, just like the case above, though I didn't spot them on the datasheet that I looked at. If that's the case, your theory of diode limiting voltage seems to make sense. The problem I have is, if this is the correct explanation, the datasheet does not need to state -0.5V as the absolute maximum rating for input voltage. It's a -11V voltage that has been (or will be) 'thrown' to the input directly without anything external in between as a buffer or whatever.

Don't get me wrong, by no means am I aiming at refuting your theory. I just find it difficult for all of these to reconcile. I've carefully checked the board; the schematic reflects the circuit correctly.

By the way, here attached a revised version with the value of the capacitor.

[Edit --- the value of the capacitor should read "470pF" not "471pF".]

[wasedadoc]

1.  Look at page 3 of https://www.ti.com/lit/ds/symlink/cd4071b.pdf to see 4 diodes in the input protection circuit of the TI version.  The max ratings section at the top of the page also shows "DC input current, any one input +/- 10 mA".

2.  On a capacitor the 3rd digit is usually a power of 10 multiplier.  So 471 denotes 470 pF.  In this case negligible difference from 471pF.  But 472 is 4700pf (4.7nF), 473 is 47000pF (47nF).

[max.wwwang]

1.  Look at page 3 of https://www.ti.com/lit/ds/symlink/cd4071b.pdf to see 4 diodes in the input protection circuit of the TI version.  The max ratings section at the top of the page also shows "DC input current, any one input +/- 10 mA".

Good to have datasheet that does show this. But in this one, it's also stated as -0.5V for the absolute maximum rating for input voltage.

2.  On a capacitor the 3rd digit is usually a power of 10 multiplier.  So 471 denotes 470 pF.  In this case negligible difference from 471pF.  But 472 is 4700pf (4.7nF), 473 is 47000pF (47nF).

Thanks for mentioning this. I did wonder what the marking "471" means. It's almost identical to this guy ---

and I looked around before marking it as 471pF. There are many webpages taking this as 471pF, like this one. So this webpage is wrong?
I don't like to take it as 471pF if it means 470 despite the negligible difference. If 470 is correct, then 471 is simply wrong.

[pcprogrammer]

So this webpage is wrong?

Yep, they got it wrong, despite the fact that they got 102, 103 and 104 mentioned with the correct values on the main capacitor page. 

I use this site mostly to lookup the values of SMD resistors, but they do capacitors too.

[TimFox]

I was curious about that ignorant website that thought "471" meant 471 pF instead of 470 pF, but my malware filter blocked it.

[max.wwwang]

I was curious about that ignorant website that thought "471" meant 471 pF instead of 470 pF, but my malware filter blocked it.

That's a testimony of the intelligence of your malware filter.

[max.wwwang]

Yep, they got it wrong, despite the fact that they got 102, 103 and 104 mentioned with the correct values on the main capacitor page. 

Thanks for confirmation. I didn't notice they got 102 and 103 right. 

[max.wwwang]

Another interesting one, similar to the previous one but only a little different. This time I want to be more quantitative.

The same question of the input voltage momentarily being -11V, far beyond the maximum rating -0.5V, also exist, if from the perspective of the U24D gate (TC4071BP). This may well be 'clamped' down to safe voltage by the internal protection diodes. But even if this is the case, to me this is the internal business of the gate but does not change the fact that its input has been exposed to an unsafe input voltage (according to the datasheet). We can park this one (because it has been discussed, and I might be too pedantic here.)

This circuit, as far as I see, works this way. The output (RHS) remains L (i.e. active H), but rises to H whenever any of the inputs (LHS) rises to H. Dur to the existence of the R/C, any rising of the three highlighted inputs will be extended from its rising edge with a constant duration (determined by RC, which is given, the L/H threshold of the gate, and probably its propagation delay).

That is, any of these three input signals, whenever it comes and however short the pulse might be, will have at least the duration of this extension on the output side. [1]

To me this is meaningful only when the width of any of these three signals may be narrower than this extension. Because otherwise this extension will only be 'buried' (as overlap) in the input pulse.

Before figuring this out, here comes a question first about the input threshold voltage. According to the datasheet, say for Vdd 9V, these two voltages thresholds , which are different (highlighted as 5.5V and 4.5V, respectively). This looks like to me that there will be a voltage range where the logic state of the input is not determined. This will inevitably happen when the input is fed with the voltage that complies with the exponential curve of an RC charging/discharging circuit. What's going to happen when the input voltage is between 4.5V and 5.5V?

[Edit]
[1] With another look, this now does not seem to be correct.

[wasedadoc]

You may be misinterpreting the datasheet but I need to see exactly how the table is labelled.  Please post a link to the original complete datasheet.

[max.wwwang]

Here it is—
https://pdf1.alldatasheet.com/datasheet-pdf/view/31643/TOSHIBA/TC4071BP.html

Please do let me know if it is a misinterpretation of the datasheet – that is very likely. Thanks.

[pcprogrammer]

The way I read it is that worst case the input voltage seen as a low is 3V but typical it will be 4.5V. This means the input has to go below this voltage to be treated as low. For it to be seen as high the worst case is as high as 7V, but typical will be 5.5V. So to be seen as high the input has to go above this voltage.

I interpret this as the gate having some hysteresis. The output will only change from low to high if one or both inputs rise above the given voltage, and will only go low again when both inputs drop below the other given voltage.

[max.wwwang]

The way I read it is that worst case the input voltage seen as a low is 3V but typical it will be 4.5V. This means the input has to go below this voltage to be treated as low. For it to be seen as high the worst case is as high as 7V, but typical will be 5.5V. So to be seen as high the input has to go above this voltage.

I read this differently.

It is fairly clear that there are three groups of columns for three different temperatures. Under any given temperature, say 25 degrees celsius, there is only one group (of columns) that applies.

In this particular group, there are two or three of the specs specified, which are "min", "typ", and "max". My interpretation is that these are for the variation between individual chips, not the range of drifting of any single chip. In other words, for any particular chip, the value for one parameter, such as input low voltage, is a single value, which is typically "typ", but may vary within the range between "min" and "max".

I interpret this as the gate having some hysteresis. The output will only change from low to high if one or both inputs rise above the given voltage, and will only go low again when both inputs drop below the other given voltage.

With the above being said, I do suspect that the discrepancy between the low and high input voltages for any particular chip, under any given temperature -- say 4.5V vs 5.5V -- indeed may mean some kind of hysteresis characteristic. But I'm not very sure.

[pcprogrammer]

I read this differently.

It is fairly clear that there are three groups of columns for three different temperatures. Under any given temperature, say 25 degrees celsius, there is only one group (of columns) that applies.

In this particular group, there are two or three of the specs specified, which are "min", "typ", and "max". My interpretation is that these are for the variation between individual chips, not the range of drifting of any single chip. In other words, for any particular chip, the value for one parameter, such as input low voltage, is a single value, which is typically "typ", but may vary within the range between "min" and "max".

That is what worst case often means, the spread across a large set of the same components. When designing a circuit you have to take this into account to make sure all devices work the same coming of the production line.

But in this case only the extremes are specified for the two outer temperatures. Typical is only given for 25 degrees. This can mean that this typical value varies over temperature. Will it vary to the given extremes, probably not, but I would not count on them being fixed on the typical value over a wide temperature range.

With the above being said, I do suspect that the discrepancy between the low and high input voltages for any particular chip, under any given temperature -- say 4.5V vs 5.5V -- indeed may mean some kind of hysteresis characteristic. But I'm not very sure.

It is not specifically mentioned in the datasheet, but if it would not have some hysteresis, you can get very weird behavior due to signal noise, where the output could flip many times before getting stable.

[wasedadoc]

With 10 volt supply and at any of the 3 temperatures an input of 7.0 volts or more is guaranteed to be treated as a HIGH by the input.  Additional info is that at 25 degrees C a typical chip will treat 5.5 or more as a HIGH input.

Similarly for any of the 3 temperatures an input of 3 volts or less is guaranteed to be treated as a LOW by the input.  Additional info is that at 25 degrees C a typical chip will treat 4.5 or below as a LOW input.

Nothing in the specs says what will certainly happen for input voltages between 3.0 and 7.0.  Any voltage up to but not including 7.0 could be treated as a LOW by an in spec chip.  Any voltage down to but not including 3.0 could be treated as a HIGH by an in spec chip.

Nothing in the specs says anything about hysteresis ie any difference in the changeover voltage when input going LOW to HIGH compared to input going HIGH to LOW.

[max.wwwang]

After the bouncing of views, I now tend to agree that the different voltages for input low or high are meant for guaranteed values for low or high. These are for assurance of the logic output. In reality, there will be only one single threshold voltage for both, but for this threshold, 1) there will be a spread of this between chips; and 2) input voltages that are not far away from this voltage may result in bouncing on the output, which is normally not desired.

Hyperesis characteristic is unlikely if it is not specifically stated in the datasheet (it seems too significant not to be addressed.)

In other words, in theoretical analysis – and yet practically (this sounds paradoxical!) – the mean of these two guaranteed thresholds [that is (4.5+5.5)/2=5V] may be used as the threshold for low/high.