Programming (non-JTAG) MAX7000 devices

[jgustavoam]

Hi guys ,

YouTuber Gerry has released another video, showing the capture of signals from the EPM7128SLC84 pins during the erase process.

He hasn't developed a parallel programmer yet.
But he commented on our project and praised our work. And he shared the link to the EEV Blog forum.

I appreciated him sharing the videos, as they really helped me a lot in understanding the programming processes for the Altera MAX7000S devices.

The video excited me - let's develop the JTAG Unlock for the EPM7128SLC84.


https://youtu.be/-Q-mtVItndY?si=OXS9DJ3oLzMKtV-N

[abyrvalg]

For EPM7128SLC84 I can see the erase pin switching sequence in ALL-07 software (and it it the same as for 7032S - shift all zeroes into A0, A1, set TM, set BE, clear NTPW, wait, set NTPW, set MT, clear BE, clear MT, clear TM) and programmer-side pin numbers for these signals, but there is no public schematic of the adapter being used for this chip (the name is "ADP-EPM7128E-PL"), so no way to track programmer pins to chip pins for now

[ukamak]

For EPM7128SLC84 I can see the erase pin switching sequence in ALL-07 software (and it it the same as for 7032S - shift all zeroes into A0, A1, set TM, set BE, clear NTPW, wait, set NTPW, set MT, clear BE, clear MT, clear TM) and programmer-side pin numbers for these signals, but there is no public schematic of the adapter being used for this chip (the name is "ADP-EPM7128E-PL"), so no way to track programmer pins to chip pins for now

What we can do is compare captures and for some pins get the function. Example with EPM7128s plcc84, 48uxp use the adapter EPM7128S@84 and we have the pinout. 
WE have a capture of EPM7032s with correct names:

and second capture is on some pins of EPM7128s plcc84 in order to have one idea of how to do.

[abyrvalg]

Yes, there are many matches - SCK, SK, SS, SDINx patterns are visible.

Or another idea: there are all "puzzle pieces" for 7064SLC84 (sw and adapter schematic on the French site), it is PLCC84 too, perhaps it has the same pinout (except the additional SDIN/SCO/SDOUT of 7128). I've tracked 7064SLC84 from sw to programmer pins, then to adapter schematics and to chip pins:

Name	EPM7032LC44	EPM7032SLC44	EPM7064SLC84
A0	39 B19	-
A1	38 B20	-
A2	37 B21	-
A3	36 B22	-
A4	34 B23	-
A5	33 B24	-
A6	32 B25	-
AINA	-	39 B19	36
AINB	-	38 B20 TDO	37
AINX	-	37 B21	41
ACLK	-	32 B25	31
NTPW	1 GCLR1	1 GCLR1	1 GCLR1
MTIN	2 OE2	2 OE2
SCK	4 A1	4 A1	79
BE	7 A4	7 A4 TDI	14 TDI
BEM	8 A5	-
SS	13 A9	A9 TMS	71 TDO
SBI	16 A11	16 A11	71 TDO
TM	18 A13	18 A13	68
SK	43 GCLK1	43 GCLK1	83 GCLK1
MT	40 B18	40 B18	67
Vpp	44 OE1	44 OE1	84 OE1
SDINA	5 A8	5 A8	20
SDINB	41 B17	41 B17	39
SDINC			46
SDIND			65
SDOUTA	19 A14	19 A14
SDOUTB	26 B30	26 B30
SDOUTC	-	-
SDOUTD	-	-
SCOA	21 A16	21 A16	4
SCOB	24 B32	24 B32	23 TMS
SCOC	-	-	62 TCK
SCOD	-	-	81

ukamak, could you check if anything matches your EPM7128S capture?

[ukamak]

Still working on EPM7032s , bud I did some test for EPM7064s

Looking a this pin table

We did a erasing capture of EPM7064s with logic analizer.
   
Pulseview capture 
 erase.7z (5.59 kB - downloaded 25 times.)
Only need to interchange SS/BI with BV. NTPW seems ok, don't know about BE,BEM,BP,BV,CB... others pins seems correct.

All is provisional like always.

[jgustavoam]

EPM7032S tests with Old PC - Quartus 13.0 Sp1 + Byte Blaster LPT1:

In order to find out more information about the EPM7032, today I am running tests using an old PC with Windows 7.
In 2024 I assembled a Byte Blaster interface that uses the LPT1 printer port for communication.
The programming in this case is JTAG using Quartus 13.0 sp1.

I managed to program my EPM7032S (Chip 4) using the Counter_sync_16 project.
I made several captures with my Kingst La1010 logic analyzer, because the other Chinese logic analyzer was interfering with the communication and preventing the tests.

Since communication on the printer's parallel port is slower, it became much better for visualizing the bits and bytes during communication!

If you want to view the captures, install the Kingston program. Unfortunately, PulseView does not yet support this logic analyzer.
https://www.qdkingst.com/en/download

In the right-hand sidebar of the Kingst program, select the JTAG decoder.

[ale500]

I just saw that Gerry, from Behind the code, did a capture of the erase sequence of the EPM7128. It would be great to get hold of the capture data. Determining which pins are the inputs and which the outputs will be a bit of work but after that one could modify your program, I mean Gustavo's program, to talk on all 8 channels.

[ukamak]

I talked with Gustavo , and we will buy some devices to test.

[jgustavoam]

EPM7032S - Programming with MAX Plus II V9.3:

MAX Plus II is a program from Altera that was developed almost 30 years ago.
It was used to program CPLDs. The predecessor to Quartus.

Max Plus II V9.3:
https://archive.org/details/1999-altera-max-plus-ii-93

Max Plus II - getting started manual:
http://www.ece.ualberta.ca/~elliott/ee552/AlteraDoc/maxplus2_getting_started.pdf

Using an old PC with Windows 7 installed, I was able to run the program.
I connected a Byte Blaster - JTAG interface that I assembled to the LPT1 parallel port (see previous topic).

One function that prompted me to perform these tests was EXAMINE, which does a complete Reading of the CPLD.
This function is disabled in Quartus.

For the Programmer to function properly, it was important to install the correct drivers for Byte Blaster.
I used the Quartus 13.0 driver. Run the bblpt.exe program to install the drivers.

Code: [Select]

C:\altera\Quartus13.0\quartus\bin>dir bb*
 O volume na unidade C não tem nome.
 O Número de Série do Volume é DAAF-F4A4

 Pasta de C:\altera\Quartus13.0\quartus\bin

12/06/2013  23:49            11.264 bblpt.exe
               1 arquivo(s)         11.264 bytes
               0 pasta(s)   32.269.205.504 bytes disponíveis

C:\altera\Quartus13.0\quartus\bin>

To perform the tests with the programmer, I used a POF file from the Counter_sync_16 Project, which was compiled in Quartus 13.0.
With the programmer window open, click on Select Programming file.

I have attached the Kingst Logic Analyzer files.
If you want to view the captures, install the Kingston program. Unfortunately, PulseView does not yet support this logic analyzer.
https://www.qdkingst.com/en/download

In the right-hand sidebar of the Kingst program, select the JTAG decoder.

Programmer HW Setup:




EXAMINE Function  - EPM7032S - CHIP4 :




Program - Counter_sync-16 POF file  - EPM7032S - CHIP4 :




Verify  - Counter_sync-16 POF file  - EPM7032S - CHIP4 :




Important information: The Max Plus II V9.3 supports the Altera LP6 programmer (parallel programming).

[fotoopa]

Hello everyone, I am fotoopa and have been following this topic for quite some time. I am over 82 years old, and my memory sometimes fails me.
I have been developing hardware for years and have worked extensively with Altera chips. Most versions of Quartus software are now installed on my computer, as well as the Max Plus II V9.3 version. I use Windows 11 as computer.

I own many types of Altera boards and also have a few old chips lying around.
These are:
EPM7064AELC44
EPM7064SLC44
EPM7032LC44
EPM7032TC44
For the LC44 versions, I have created a setup that allows me to perform measurements on the JTAG pins. For this I use the Picoscope 3206D version 200 MHz with 16 channels logic analyzer. My logic analyzer does not contain a JTAG decoder, but I can view certain data via an SPI protocol.

This topic is also very interesting to me. I may be able to share some test data.
For the EPM7032LC44, I also need to use the very old version of the software, Max Plus II V9.3.

My current setup:
EPM7064AELC44-10 test pcb by Frans, on Flickr

My stock of Altera ICs:
ALTERA_FPGA_devices by Frans, on Flickr

With the MAX Plus II V9.3, I still need to try writing a small piece of code or a schematic entry version. For now, I haven't been able to compile it to see if it works for the EPM7032LC44 version. I can't compile this EPM7032LC44 with Quartus 13.1 because the EPM7000 series is not available.

I now see that my USB Terasic Blaster does not work with the old MAX Plus II V9.3 software. For the time being, I see no solution for programming the EPM7032LC.
I don't see a solution for making the parallel programmer compatible with the Arduino board either. I have an Arduino Due version and your code doesn't compile without errors. My knowledge of C language is insufficient to fix this.
I have lots of photos on my Flickr website: https://www.flickr.com/photos/fotoopa_hs/
There you can see what I've been making over the last few years.

Frans.

[ukamak]

Hi all ,
With jgustavoam We're working on arduino project. Since I'm an amateur programmer, I'm sure there are many things that could be improved.
The project's goal was to be able to erase the chip, but now, for the EPM7032s, we can already erase it, retrieve the silicon ID, and program part of the data; the last part is still missing.
The desired option is selected through a terminal.
In erase_w002.h, the serial port can be changed in a define statement. By default, it uses serial 0 "usb".
For now options 1 to 5 is for EPM7032s PLCC44 and 8 for EPM7032 PLCC44

[ukamak]

Hi fotoopa ,

Welcome aboard! Many of us here are beginners, but we're eager to learn
We've already programmed part of the EPM7032s, and I assume the EPM7032 will be the same.  We still need to study the upper part, as it's programmed differently.
I'm glad to see that at 82 years old, you're still enjoying tinkering with electronics!

[fotoopa]

Hi ukamak,

Thanks for the replay!
To use the Arduino mega2560 program, I would first need to purchase this board. Then I could have the same setup. It's a shame that my Arduino Due isn't compatible. Those Arduino boards, yes, I already have several, but I use them so little. Okay, they do have it in stock. It would be here in a few days. I've already compiled the program for the Mega version 3 without errors.
I can program all my 7000S versions via JTAG, but I would still like to test the non-JTAG ones. Just to keep myself busy.

[ukamak]

@fotoopa,
About arduino due , it's ARM  cpu and 3v3 , for now we use AVR cpu and 5v I/Os. To use arduino due need to port the software and add buffers to comply with 5v I/O.
Nice photos , You had a lot of fun doing projects. You have also intronix logicport?

[fotoopa]

@fotoopa,
You have also intronix logicport?

Yes, but I rarely use it anymore. It has a too small memory buffer, which means you can't make deep recordings using a high clock frequency. One advantage is that it has 32 channels. I also have two other PicoScope devices, including the USB PicoScope 2406B 4-channel 50 MHz. It also has large memory buffers that enable deep recordings.
The scope currently in use is the USB Picoscope 3206 MSO 200MHz with 16 digital and 2 analog inputs. It has sufficient internal memory.

I'm going to order the Arduino Mega 2650. That will allow me to follow your tests.

[jgustavoam]

Hi Fotoopa,
Welcome to the forum.

I also enjoy this type of project because it's a great challenge. We've already discovered part of it.
I hope to count on your help and experience as well.

I'm an electronics specialist, and this year I'll be celebrating 50 years of study. Next month I'll be 66 years old.
But CPLDs and FPGAs have always been a mystery to me. And with this topic, I'm finally able to learn something about CPLDs.

I have considerable experience with microcontrollers - Arduino, ESP32, Raspberry Pico. Let me know if you have any questions.

https://docs.arduino.cc/hardware/mega-2560/

https://www.arduino.cc/en/software/

I used to be a subscriber on Flickr. Not anymore.
https://www.flickr.com/photos/jgustavoam/

Regards,

Gustavo Murta

[fotoopa]

Hi Gustavo,
Nice to meet you. You're still much younger than me! Usually, you can still enjoy a lot at this age. You have more time, and these tests are great to do. I'm following everything with excitement.

I'm going to buy that Arduino Mega 2560 board first. I had initially considered the cheaper clone version, but I'm going to buy the original version after all. All my older boards have always been originals.
I also have a few ESP32 boards and the Raspberry Pico. But I've always preferred working with FPGA boards. I have at least 15 of them here. Some are in use, the others are on my desk upstairs. I have plenty of space there, but in recent years I've been working downstairs in my small room.

I have had diabetes for 40 years and need to have regular checkups, especially as my eyesight is deteriorating. On Wednesday, I am scheduled to receive my 51st injection in my eye. Despite all this, I am still able to conduct small experiments and follow what others are achieving.

I used the EPM7192 extensively in hardware designs in the late 1990s, along with many GAL chips. This was hardware for controlling industrial machines with many VME 6U boards. Later, I used Altera Flex10K200 chips with PCI boards. That was still schematic entry, many pages of schematics with my own libraries. I have been retired since 2004.

The Arduino Mega 2560 board is indeed 5V. This is simpler than having to use level converters again. In total, I have three CPLD chips: one EPM7032LC44 and two EPM7032TC44. With some effort, I was able to solder one of the EPM7032TC44s onto a test board. I still need to finish it up on the breadboard, and then it will be ready to test with the Arduino. I expect to be able to use the setup by the end of this week. I will definitely share my results here in this thread.

Frans.

[fotoopa]

@Gustavo,

Is this the latest version of your Arduino Mega program:
EPM7032S Parallel Programmer - ERASE Version 10

My Arduino Mega board 2560 should arrive today, and I would like to start measuring with your program. That is why I would like to work with your latest version. I connected the EPM7032TC44 to the breadboard.

[jgustavoam]

Hi fotoopa,

I'm organizing the project on Github. There are some photos there.
The programmer needs a 12V power source.
I used Wire Wrap  30AWG - 8 Colors
I suggest starting the tests with READ CPLD - EPM7032S.
Let me know if you have any questions.

https://github.com/Gustavomurta/EPM7032_CPLD

[fotoopa]

Hi Gustaavo,

Thank you for your wonderful and extensive additional information. I have saved your GitHub link. As for the power supply, this is not a problem. I have two Korad 30V-5A power supplies here on the table. First, I'm going to read out the Mega board signals with the scope. I just received an email saying that they will deliver my Mega board today. I don't have a 7032SLC44, but I do have a 7064SLC44. I will have to investigate further whether I will be able to test that. I have the transistor and the MOSFET to control the 12V.

Update:
The Arduino board has arrived. I connected it and everything seems to be working. Tomorrow I will perform the first measurements with the scope.

[jgustavoam]

EPM7128SLC84 - Starting studies:

Ukamak and I are beginning our studies on the EPM7128SLC84.

I'm adding content to my Github:
https://github.com/Gustavomurta/EPM7128S_CPLD

Incomplete and possibly incorrect information about the pinout of this CPLD.

CORRECTION!!! - This pinout is probably for the EPM7064 (4 LABs)! Remember that the EPM7128 has 8 LABs.

I based my diagram of the chip on this pinout.




Incomplete diagram. I have no idea what the function of the extra pins is, which are different compared to the EPM7032S.
CORRECTION!!! - This pinout is probably for the EPM7064 (4 LABs)! Remember that the EPM7128 has 8 LABs.




Complete diagram based on the Altera datasheet (JTAG Mode):
This pinout is the same for EPM7128SLC84 and EPM7064SLC84.

[ale500]

That looks great !

If the 7032 can be erased using 2 serial input/output pairs (triplets?), and here is the jtag enable bit too, one could speculate that only two channels are also enough for the 7128.

I think I will try that, needing full erase maybe be required, may be not. Everything we need, the ones with locked chips, is to enable JTAG.

Thanks again.

[Beta_vulgaris]

EPM7128SLC84 - Starting studies:

Ukamak and I are beginning our studies on the EPM7128SLC84.

I'm adding content to my Github:
https://github.com/Gustavomurta/EPM7128S_CPLD

Incomplete and possibly incorrect information about the pinout of this CPLD.

I based my diagram of the chip on this pinout.

(Attachment Link)


Incomplete diagram. I have no idea what the function of the extra pins is, which are different compared to the EPM7032S.

(Attachment Link)


Complete diagram based on the Altera datasheet (JTAG Mode):

(Attachment Link)

The diagram I made earlier was based on Matthieu Benoit's ALL-03 ADP-EPM7064 schematics and MQP AD359, probably also Dataman/Advantech Labtool-48.

[ale500]

 @Gustavo: both pictures use pin 78 as GND and +5V.
78 : is VCCIO
82 : is GND

Using one of my EPM7128S I tried ukamaks suggestion from page 11, pulse BE and TM while holding OE1 at 12 V didn't work. I only connected SS to ground, the other pins are floating. With it didn't work I mean, the JTAG is not re-enabled. TMS is still an output, one see contention on TMS.

I will (painfully) ground all the other pins and try again.

[jgustavoam]

Ale500,

Sorry my mistakes. I think I was tired.
I will correct the identification errors.
Thank you for letting me know.