bond wires used to be pure gold, but now were changed in the whole electronics industry to pure copper.
aluminium is always used for the top chip metallization, and the bond landing pattern .
On that photograph, obviously LT uses aluminium bond wires.
Afaik, this material is used in power semiconductors also, therefore low resistance may have been the argument here.
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I doubt they used aluminium bond wires unless the chip metallization is known and this is not gold (see the picture), what you would need for an aluminium bond wire.
Excuse me, branadic.. I receive PCNs (Product Change Notification) every day, from all relevant semiconductors suppliers worldwide.
So I can tell for sure, that for the chip metallization, usually and definitely aluminium IS used!
This is only true if the bond wire is gold. You can't bond an aluminium wire to an aluminium surface, sorry but I studied microsystem technology and still work in a field where bonding is one way to connect bare dies to a pcb or mid
I was very surprised when testing the VRE3050AS reference which is in a hermetically sealed package with gull wing leads. In this case I thought that the influence of the PCB to the chip would be negligible. But this was not the case. I measured values from -16 to +186 uV against untwisted PCB.
Other references have other values depending on construction and individual make.
A LT1236ACS8 gave around 400uV between minimum and maximum value.
... The TO-style metal cans are 100% immune to mechanical board stress. More than likely, the slots in the PC board were to reduce heat-loss, and (in turn) reduce power consumption when running on battery for the 4910 reference. I am guessing that the engineer at Datron that designed this left the company, and then following engineers simply copied the design without understanding why. The "A" version of the LTZ1000 did not show up for a while-- so Datron only had the LTZ1000 to work with-- and it is going to use more power for the heater than the "A" version-- thus the need to not only reduce heat loss through the PC material, but also to insulate the LTZ1000 with foam.
You can use slots on your LTZ1000(A) design if you want-- this will reduce heater power a very small amount (and even smaller on the "A" version). If you intend for your reference to run on battery power for extended periods of time, this may be important to you. If your reference is line-powered only, then I just don't see any benefit to the slots.
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And there you have it... 'nuff said...
This is kind of interesting. The 0.05ppm/C figure comes from the original Ap-Note. So, the temperature sensing transistor will have about -2mV/C response. Using the original circuit in the Ap-Note, many experimenters have found that the ouptut voltage of the LTZ1000(A) will have ~50ppm/C drift with the oven not used. This means that to achieve the 0.05ppm/C performance we have to maintain the die temperature +/-0.001C.
The 0.3ppm/year stability figure is for the original circuit-- perhaps running the die at 45C. If you drastically lower the die temperature (to say, 0-deg-C), then you might expect long-term drift to be far less than that-- perhaps as low as 0.1ppm/year (on selected devices of course-- the "average" device will be slightly higher). This can be done using a multi-stage Peltier device to chill the case of the LTZ1000(A) to -10C, then run the on-chip oven (which has superior temperature control over the Peltier device controller) at 0C. The results should be quite striking-- almost "spooky" JJA-like stability...
If this is true you should have no change using the LS8 package right?
Most PC board materials exhibit piezoelectric (and/or triboelectric) effects with mechanical stress
No-- I have seen no study with a statistically large enough population that would indicate to any level of certainty that my assertions are correct. However the Spreadbury study did produce some interesting results [see figure 4 in the attached file], and if you can believe the theory that the drift of the LTZ1000 chip will be reduced by 1/2 with each 10C lowering of die temperature, then it is worth an experiment.
It is possible that this theory is wrong, or that there are other limiting factors that would prevent such low levels of annual drift-- only experimentation with hundreds of units over several different wafer lots would prove this-- and this would take a great deal of money and a great deal of time-- perhaps at least 3 years--
The only thing we can do as hobbyists, is build a few of these, and see how they drift against each other-- not as good as having a JJA, but it would tell us something at least.
No I do not-- I was reading about it on the Internet a few weeks ago, and silly me, I did not bookmark the page-- and I am too lazy to try to search for it-- but, if *you* find it, post a link and then we can all enjoy it-- (and I will read it again-- my memory is not as good as it used to be when I was younger).
This quick and dirty test is no proof, I have to admit.
Are you certain that it was package stress causing the shift in output voltage?
I could believe this with an epoxy package, but not the LS8 (ceramic LLC)-- can you make a movie of this and put it on YouTube so we can all enjoy it?
FEA simulations usually exaggerate displayed deformations so it can be visualized.
Our laboratory researches wasn't confirmed the insensitivity of the LTZ1000 to mechanical (thermo-mechanical) stress. Output voltage drift is small, but measurable even in 7.5 digits mode and well explained via strain compatibility conditions of LTZ1000 and PCB's.
FEA simulations usually exaggerate displayed deformations so it can be visualized.
What about the strain gauge effects (resistance change) of the conductors as being the primary cause? Either circuit board traces, chip leads, or chip die level.