zofz,
Very impressive work you have done, this project saved my life (well at least countless hours trying to trace the board and check/compare footprints, component orientation, etc), was working on a project that was made by a very good programmer, but as we know most programmers assume that you "know all", and in the end I had somewhat broken bom, pdf with schematics and gerbers with poor silkscreen with no outlines for component orientation.
It would be very nice if you will have free time and of course if it's possible to link Altium generated schematic PDFs to gerber viewer, so you can click on part in pdf and it shows on which two pads you need to solder the part when you have 6x6 matrix of identical pads which has no outline to show you on which two pads to put the part
P.S. it would be nice if you could setup some donation system (maybe paypal), so the guys and gals can support your work, as we know these things consume lots of time and you need to pay your bills...
Best Regards,
Mantas.
Hi,
It is a really impressive software.
And non of pricey tools have similar nice 3D capability (except Zuken CR-8000 for 100000$).
But I'm in trouble with long name files.
I couldn't recognise layers manually as you can see on the picture.
Any possibility to port to Linux?
I'm in the process of migrating completely to Linux and I will really miss ZofzPCB.
I have not been seeing the GUI crash, finally I have corrected 2 bugs.
.....on one of my boards (still under dev) the silkscreen on the underside happens to cross directly over some THP's. From the topside looking through the holes you can see the silkscreen jumping across the pad......should really be broken by the pad/hole.
I quickly tested with
https://github.com/FPGAwars/icezum/tree/master/src-kicad
and used Altium File names.
.....on one of my boards (still under dev) the silkscreen on the underside happens to cross directly over some THP's. From the topside looking through the holes you can see the silkscreen jumping across the pad......should really be broken by the pad/hole.
Another angle is to say that is correct - usually silkscreen is pulled back from pads, and some EDA have a option to avoid pads, (I think some do this by 'plot-white') so anything that does not avoid pads (& holes), is considered an issue that needs upstream fixing.
Many thanks zofz. Nice program. Noticed using Eagle it wanted the ".dri" file not the txt drill file. Some parts not rendered properly but that's probably the IPC D 356 and eagle. now I just have to read up the help files on how to use correctly.
Wow- This is very impressive.
I quickly tested with
https://github.com/FPGAwars/icezum/tree/master/src-kicad
and used Altium File names.
It looks 99.5% ok, with some minor issues / quirks / puzzles
* Long file names do not fit in the file-views, and there seems no way to resize those ?
* I see a strange effect, where Holes with no traces, show under hover, but all those with traces show no holes ?
( The holes that do appear and tag, look fine, so the drill file must have read ok)
Looks almost deliberate, but unexpected ?
* when I enable IPC356, 3D nicely (magically!) appears in most cases, but in a one (U6) some strange slight spin is seen ?
There are some vias-as-parts (Via**) still to be cleaned in this test example, so the large area over TQFP144 is a 'false positive'
Addit: I see U6 is an unusual 16 pin SO (2/6/2/6), so maybe the angle is just a fit-artifact of trying to align over that ?
It seems to have different pin-pitch on each of 2 chosen pin sides ? - so is trying to make sense of the less common footprint.
I had a look at the IPC D 356 file on parts particularly the x,y,r sizes positions. As you can see, a few parts were not rendered or are not right:
Capacitors rendered too low in height;
a few T092 transistors not rendered correctly, their tops are too low like the caps);
An IC wide SOIC16 not rendered at all; Inductor not rendered (looks like SIL pins);
JST XH 2.5mm pitch connector not rendered (base of board);
Another ZR 1.5mm pitch JST not rendered properly (near LQFP64);
Crystal HC49S not rendered correctly;
wire pads not rendered correctly (look like pins) (VIAs ok);
Image sensor ICX453AQ (large device) not rendered properly, should be on bottom "16" layer.
Is there a way I can fix these issue? I have played with Eagle 3D and POV Ray and made my own parts before. But, that might give a nice image, but it's just eye candy, it hasn't the in depth analysis and details your program has!
Don't worry about the part off the board, that's just me!
.....Now you can hide or swap THT to another side, by a right mouse click menu...
1. Board Outline file was assumed to be .gbr - it looks that it should be .gm1 - I have changed it by hand or should that be a rule?
2. KiCad generated plated and not plated drill files. Both files should be plated. I am not drilling thru the top/btm copper in a case of not plated holes, assuming the copper is not there. This is why the holes was not visible from top/bottom.
...... So obviously I have no clue what is the height of the electrolytic cap.
...
In this release I have been adding a table based library, including R and C (and L) 0603, 0802
..
In the meanwhile, I am trying to load BOM and identify columns, map components from BOM to IPC356. Unfortunately there are very fuzzy rules about component naming and component footprint naming.
Great - That's looking improved1. Board Outline file was assumed to be .gbr - it looks that it should be .gm1 - I have changed it by hand or should that be a rule?KiCad usually puts Board outline on layer Edge.Cuts
I applied the Altium naming, as that seemed to import better, so I guess that maps Edge.Cuts to some Gerber name.
2. KiCad generated plated and not plated drill files. Both files should be plated. I am not drilling thru the top/btm copper in a case of not plated holes, assuming the copper is not there. This is why the holes was not visible from top/bottom.
I'm not following this exactly ?
I would expect all holes to appear in the viewer, and if there is some means to show plated/non plated that is nice.
Even just a hover-check would be ok, but a copper/fibreglass type colour render for plated/npth would be cool...
ie a hole should not be discarded or not shown in a viewer.
In the test I did, it looked like the non-trace-connected holes did render as expected.
...... So obviously I have no clue what is the height of the electrolytic cap.
...
In this release I have been adding a table based library, including R and C (and L) 0603, 0802
..
In the meanwhile, I am trying to load BOM and identify columns, map components from BOM to IPC356. Unfortunately there are very fuzzy rules about component naming and component footprint naming.Tables and BOM mapping can give good results, but are of course more work.
Some simpler means to communicate height is needed.. I did see someone mention a nifty trick a while back, of using the Line width to encode the Height.
I just tried this in KiCad, and it saves and Gerber plots to 6 decimals in mm.
That allows line widths to .01 mm and gives up to 4 more digits for height, which could be (fixed point) any of 9.999mm or 99.99mm or 999.9mm
Pick one - perhaps 99.99mm, covers reasonable heights, and anything > 100mm can always use a 3D table, and 99.99 tolerates 5 decimal digit mm gerber files as 99.9mm . (not all PCB products can plot to 6 decimals in mm)
This could give a simple user-3D-option, whereby they can just edit their library, and not need any more associations at all.
KiCad can currently create and plot footprint info to these non copper layers
PFR_Widths-F.Fab.gbr
PFR_Widths-F.SilkS.gto
PFR_Widths-F.CrtYd.gbr
PFR_Widths-B.Fab.gbr
PFR_Widths-B.SilkS.gto
PFR_Widths-B.CrtYd.gbr
Q: Is there enough info in the IPC356 and gerber files to relate outline info to a component ? My guess is no ?
I'm wondering about the best way to extrude here...
I see Kicad can remove Silkscreen over Pads, which it does by a simple dual plot process in one file
first Outlines at %LPD*% (Plot Dark),
then Pads(mask) at %LPC*% (Plot Clear) to remove any silk outline info within the pad regions
That could allow an outline on Silk layer, (safely removed over pads), but the pre-removal outline is fraction-scaled-extruded to give height.
User would nominate the Gerber file containing the (fractional encoded) height info, and the rest is simple software ?