"NU180" - A U180 drop-in replacement for the 3458A.

[Barry Ward]

I get it.   I was poked when you mentioned tempco.  I've spent many hours in front of the chambers.....

[Zondar]

A few questions:

Where in the machine, or how, is the CAL175 temperature measured? I have a temperature probe on my previous board and find a substantial difference between that value and the temperature at the board (not unexpected). The temperature delta at the board is almost 2x the delta of CAL175 (which is distinctly higher in temperature, too). TCR's on the board would respond to the temperature at the board, obviously, rather than that of CAL175, so I wonder about pertinence.

What is the correct formula to compute temperature drift in ppm/C from CAL72? Is it just (cal72_1-cal72_2)/(temp1-temp2)*1,000,000? Adjust by dividing by cal72_1 as well? Is there another factor of 10 in there due to the 10V scale?

Also, what are people's experiences with the rising clock edge to date? I think most people are using the falling edge right now. Is it clear yet that we should stick with that?

Thanks.

[Barry Ward]

did not want to hijack so....Here's my question about internal temperature (Not directly related to the U180 project)

[TheDefpom]

Well, I have been watching this thread from afar for some time now... thinking that one day it will be something I need, despite not owning a 3458A.

A couple of weeks ago I purchased one that was apparently working OK, was calibrated 2 years ago at Keysight, it arrived last week and I immediately started testing, and found it was drifting over 20ppm a day... and was getting worse day by day, this morning has failed with 202 error... sigh.

I wanted to join 3458A club... not the broken 3458A club.

[Zondar]

That sounds like a classic U180 failure, so join the fun here and build a board! 

You can find KiCad files for one of the latest designs at the bottom of the first post of this thread. It's a known-good design by now, though there will be some changes made to it soon.

[KE5FX]

I wanted to join 3458A club... not the broken 3458A club.

The reverse engineering progress made by Zondar and others actually gave me an excuse to pull the trigger myself a couple of weeks ago.  The one I bought seems fine, (un)fortunately, and has already been put to good use.  It is nice to be able to see OCXO tuning voltages at the sub-uV level, and to be able to delve into low-level drift behavior that might or might not be due to the voltage reference. 

I should've picked up one of these long ago but I didn't want a research project in the event of a U180 failure.  Thanks to those who are putting in the effort!

[Zondar]

Also, what are people's experiences with the rising clock edge to date? I think most people are using the falling edge right now. Is it clear yet that we should stick with that?

Thanks.

Is there a clear resolution to the clock edge question, or is that still being investigated? I've put aside my stubbornly non-functioning V0.4 board for now in favor of updating the design.

[DB4UCH]

Is there a clear resolution to the clock edge question, or is that still being investigated? I've put aside my stubbornly non-functioning V0.4 board for now in favor of updating the design.

No, I don't think there is a clear resolution yet, as running the FFs and CPLD with inverted CLK is more stable than running them without it, but I don't know how much this stability improvement is down to the delay that is added by the inverter vs the inverting itself.
I will try to just install a buffer on my future v0.4.1 (with switched around references) and see how this behaves.
KiCad files and schematic attached below (for this v0.4.1), I will order the PCB for this new revision soon.

Greetings,
Simon

Edit: I updated the design slightly (added another C) (attached below) and ordered a new set of PCBs.

[Zondar]

I've updated the V.0.4 layout to V.0.5. So far the changes include:

* Changed switch configuration to MiDi's.
* Changed from VDD1 to VDD2 for the switches associated with the external FF (U1 and U2). This more or less mandates the use of 3.3V for the FF. I left in the voltage selection, though.
* I left the other two switches at 5V (VDD1) for now. This can be reconsidered.
* Moved U1 and U2's decoupling capacitors to the front. So far I couldn't manage to do so with the last two.
* Changed the series resistors from the FF to 805's for easier hand-soldering (we have changed those often).
* Removed the useless 0.1uF's from the main voltage inputs.
* Added another 805 (e.g. 10uF) for VDD2. I wonder if an even larger footprint should be used for these.
* I haven't changed the clock distribution yet, pending clock edge discussion.

I still have my combo-resistor footprints in place. I can change those to 805's only if that's what other people are committed to. There would be enough space to double those up if desired, but I'd leave that up to you.

The layout is error free (assuming my schematic changes are good) and ready to go in principle. But what other changes are desirable, or what comments might people have?

Edit: Simon made a revision too and posted while I was typing. We chatted a bit about the differences. I'm going to make a revision to the CPLD's control lines to match his configuration so that we can still use the same code. I've deleted my schematic and layout for the moment, and will repost them later when I'm finished with that.

[wanghar]

Some progress updates. My new revision of the PCB was assembled yesterday and tested on the unit. Here are the initial results compared with another 3458A: the temperature coefficient (TCR) difference is about 0.4 ppm/K, which shows significant improvement over the previous version. INL comparison with the 3458A shows a stable difference of less than 0.1 ppm in the 0 to +10 V range, and about 0.25 ppm in the 0 to -10 V range.

The main changes in this version are in the selection of precision resistors:

One pcs of LT5400-6 (5K/1K/1K/5K) is used as the 7 V to 12 V step-up resistors.

One pcs of LT5400-1 （ 4 *10K ）is used as the +12 V to -12 V conversion resistors.

Four 80 K metal foil resistors and two 100 K metal foil resistors (paralleled to 50 K) are used. Due to space constraints, the four 80 K resistors are through-hole mounted on the bottom side, while the two 100 K resistors are laid flat and soldered on the top and bottom sides respectively.

Noise performance is similar to the previous version. The temperature coefficient still needs longer observation via CAL72.
A -2 µV offset is observed in the -2 V to -10 V range, which appears to be the main cause of the 0.25 ppm INL difference in that region. The cause is not yet determined, but it is different from the earlier gain error issue. No errors 114 or 202 reported.

Edit on March 08, 2026:

I've now populated and assembled three boards of this revision. In comparative testing against another 3458A, two of them show INL within 0.25 ppm, but one board stubbornly sits around 0.7 ppm. I've tried swapping out the ADG734, the flip‑flop, even the CPLD, but nothing made a real difference. So there's still some degree of uncertainty with this design.

Noise performance is pretty close across all three boards with input shorted: around 0.86 µV at 1 PLC, 0.35 µV at 10 PLC and 0.13 µV at 100 PLC RMS. For temperature coefficient, the best board is about 0.3 ppm/K worse than the reference 3458A, while the worst one shows a difference of roughly 0.7 ppm/K – this seems tightly linked to the TC matching of the four 80 kΩ resistors.

A key mechanical note: this PCB must be used with a specific PGA65 socket soldered onto the A3 board. The socket needs to have cut‑out openings where there are no pins – exactly like the one in the attached picture. Otherwise the four 80 kΩ metal foil resistors will physically hit the socket and you won't be able to install it. Definitely keep that in mind.

Besides that mechanical constraint, another issue seen on this rev is a noticeable offset when using a GPIB adapter (cloned Keysight 82357B), particularly at 1 PLC. The root cause is still unclear.

New added the Gerbers, BOM list, CPLD firmware file(svf) as attached. for reference.

[Zondar]

Impressive results! This very, very close to a fully satisfactory replacement!

I paused my own respin, partly because I didn't understand some of my measurements, most particularly temperature sensitivity. I tested two boards, one with high quality thin-film resistors with generally 0.1-0.01% values and 2-10 ppm/C TCRs, and one with premium quality foil resistors purporting 0.01% and 0.2 ppm/C. The TC I was getting using CAL72 was between 7 and 15 ppm/C, depending on the board and whether I was using the board's temperature or the CAL175 temperature. There was no clear improvement from the use of foil resistors, which if anything was worse. My numbers were an order of magnitude or more higher than all others have measured. Either my technique is wrong, or ... what? 

[aronake]

To bring down TC, maybe what is needed is to to TC measurements on many resistors and then select those that would have approporaite TC. And if TC on the U180 replacmenet is still off, figure out what resistor need different TC and replace this with one that have TC in the desired direction.

I could see that the U180 have same benefir for its resistors as the resistors in TDP1603 i.e. produced out of same batch of resistive material. It may then mean that TC for each resistor is not too great, but they all have same TC. Problem with mouting PCBs with resistors is that the resistors come from all different batched with different TC. Individual temp scan of the resistors would help here.

Just an idea...

[Kleinstein]

Using resistor array could solve some of the resistor TC matiching. However 80 K is not a standard value and matching to 50 K for the input would also not work easy. There is a work around, by changing the reference from +-12 V to +-15 V and than have 100 K instead of 80 K. I have mentioned that before.

If one wants to trim the TC, the 7 to 12 V part would probably the best position, as here the resistor ratio is not so critical (could be a few percent off nominal). At other positions one would still have to keep the resistor ratios pretty accurate. The 50 K for the input would be a possible point too, but this resistor needs low TC to avoid thermal nonlinearity.

[Zondar]

My 50 and 80k's were custom made from the same batch of foil resistors, specifically so that they might match better.

To measure TC, during the day (warmer), I took 3 readings of CAL72 and CAL175, plus from a thermocouple attached to my board, and averaged them. Then, early the next morning (cooler), I repeated the measurements. I repeated this whole procedure twice. There was about 7.5 C maximum change in the thermocouple measurement, and a delta of 4.7 C for CAL175. (The machine had its covers off, with the board exposed.) Then, calculate TC_ppm=(cal72_2-cal72_1)/(temp2-temp1)*1,000,000/cal72_1). Is there a problem with this somewhere?

[MiDi]

Some progress updates. My new revision of the PCB was assembled yesterday and tested on the unit. Here are the initial results compared with another 3458A: the temperature coefficient (TCR) difference is about 0.4 ppm/K, which shows significant improvement over the previous version. INL comparison with the 3458A shows a stable difference of less than 0.1 ppm in the 0 to +10 V range, and about 0.25 ppm in the 0 to -10 V range.

The main changes in this version are in the selection of precision resistors:

One pcs of LT5400-6 (5K/1K/1K/5K) is used as the 7 V to 12 V step-up resistors.

One pcs of LT5400-1 （ 4 *10K ）is used as the +12 V to -12 V conversion resistors.

Four 80 K metal foil resistors and two 100 K metal foil resistors (paralleled to 50 K) are used. Due to space constraints, the four 80 K resistors are through-hole mounted on the bottom side, while the two 100 K resistors are laid flat and soldered on the top and bottom sides respectively.

Noise performance is similar to the previous version. The temperature coefficient still needs longer observation via CAL72.
A -2 µV offset is observed in the -2 V to -10 V range, which appears to be the main cause of the 0.25 ppm INL difference in that region. The cause is not yet determined, but it is different from the earlier gain error issue. No errors 114 or 202 reported.

Very promising results!
Nice use of the LT5400-6 for the boost to 12V, saves some space compared to osop solution, but might not work for all reference voltages (limit of cal values).
The onboard compensation of ZR_LO current is clever, would be even better to remove R168 and compensate just onboard!
The constant -2µV offset for negative voltages is strange, how do you calculate the INL, could you provide the raw measurements?
Could not come up with any part of U180 that could result in a constant offset only on one side of 0V - AZ corrects all offsets inside the AZ loop.
If just looking at the INL for each side, the differences are probably covered by noise.

Hard to follow 28 pages, would be nice if you could provide a link to your last version.
Could you please provide the bom of the build? E.g. what resistors are used for ladder, resistors to control input of switches and other parts that deviate from schematic.
Could you please give some detail on noise level, the used settings and duration of observation?

[Kleinstein]

The 5k 1K  LT5400 would give a perfect 7 to 12 V gain as 5 K and 7 K. For an ADR1000 ref. with 6.6 V to start with one may want a different ratio. 5 K and 6 K may actually work, so just bridge out 1 resistor.
For the current compensation one could change R168 (to 12 K) or add a resistor (some 65 K ?) for additional ground current to the NU180 board.

[wanghar]

Nice use of the LT5400-6 for the boost to 12V, saves some space compared to osop solution, but might not work for all reference voltages (limit of cal values).

Using the LT5400 still offers a good chance to cover most of the calibration voltage ranges. When ZR_HI < 7.15V, the 7K/12K combination from the LT5400-6 yields a +vref12 no greater than 12.25V. If ZR_HI > 7.15V, a LT5400-7 with its 7.5K/12.5K combination can be used to achieve a +vref12 around 11.9xV, which should also be within a suitable voltage range. For a 6.65V ADR1000, configuring the LT5400-6 as a 6K/11K divider would produce a pretty nice +vref12 of about 12.1xV.

The constant -2µV offset for negative voltages is strange, how do you calculate the INL, could you provide the raw measurements?
Could you please give some detail on noise level, the used settings and duration of observation?

The INL calculation is based on using measurements from U180 as the reference. The difference between NU180 and U180 measurements from 0V AND +10V is used as the basis for gain calibration. Then, all voltage measurement points from -10V to +10V of NU180 are adjusted accordingly by the gian. After adjustment, these values are compared with U180's measurements to calculate the INL. Zero-offset alignment should also be performed, but since the offset difference at zero is pretty small, this step was omitted. The raw data and calculations are in the attached spreadsheet. Hopefully this data won't cause too much confusion.

The noise test followed the method previously suggested by Kleinstein: with the input short-circuited, voltage readings were collected at 1 PLC, 10 PLC, and 100 PLC（All in 10V range）. Data was received by using a Keysight 82357B GPIB adapter and RMS was calculated in real-time on DMM_tool. Each measurement consisted of 100 data points. Of course, this measurement includes the noise from the A1 board as well, but it can still serve as a comparative reference for evaluating the noise level.

Could you please provide the bom of the build? E.g. what resistors are used for ladder, resistors to control input of switches and other parts that deviate from schematic.

Since the board design is relatively simple, no dedicated BOM was generated. On the board, all 13 control resistors uniformly use 22 Ω resistors. The four pull-down resistors R39, R41, R42, and R43 are left unpopulated. U3 and U4 are powered by VDD2, so a 0603 ferrite bead is populated at R24, while the R23 position is left open. The FF chip U1 still runs on +5 V, so a 10 Ω resistor is populated at R2, and R1 is left unpopulated. In the ladder section, R16, R20 and R22 each still use two 75 kΩ (10 ppm) resistors in parallel to form a 37.5 kΩ equivalent, while R17 and R21 use 16.7 kΩ resistors with 25 ppm TCR. On the back side of the board, 0603 ferrite beads are used at R37 and R38 on the clock paths. All other components are essentially as shown in the schematic.

[wanghar]

For the current compensation one could change R168 (to 12 K) or add a resistor (some 65 K ?) for additional ground current to the NU180 board.

On this revision, a 68 kΩ resistor (R44) was used to compensate for the change in ground current caused by using the 5 kΩ + 7 kΩ resistors. Yes, changing R168 on the A3 board to 12 kΩ is also an option. Moving R168 onto the NU180 board, as MiDi mentioned, could be another good alternative.

[wanghar]

Using resistor array could solve some of the resistor TC matiching. However 80 K is not a standard value and matching to 50 K for the input would also not work easy. There is a work around, by changing the reference from +-12 V to +-15 V and than have 100 K instead of 80 K. I have mentioned that before.

If one wants to trim the TC, the 7 to 12 V part would probably the best position, as here the resistor ratio is not so critical (could be a few percent off nominal). At other positions one would still have to keep the resistor ratios pretty accurate. The 50 K for the input would be a possible point too, but this resistor needs low TC to avoid thermal nonlinearity.

If taking use of 100 kΩ OSOP or TDP1603 resistor array on NU180, the required changes would be:

On the A3 board, change R168 from 10.2K to 19 kΩ(reason see below).

On the A3 board, change R154 from 604 kΩ to 755 kΩ.

In the ZGJC section, change R185 from 3.01 MΩ to 3.76 MΩ.

Change R161/R167 from 301 Ω to 100 Ω.

If using input supply modulation, change R176 from 24.3 kΩ to 30 kΩ.

As for boosting 7.1 V to 15V, using an LT5400‑8 (9 kΩ/1 kΩ/1 kΩ/9 kΩ) configured as 9 kΩ : 19 kΩ is feasible.
The +vref 5 V could be fulfilled by an LT5400‑1 configured as 30 kΩ : 10 kΩ.
For the +15 V to -15 V conversion, an LT5400‑1 could still be OK.

These are indeed quite a few changes. Are there any others that need to be considered?

[wanghar]

To bring down TC, maybe what is needed is to to TC measurements on many resistors and then select those that would have approporaite TC. And if TC on the U180 replacmenet is still off, figure out what resistor need different TC and replace this with one that have TC in the desired direction.

I could see that the U180 have same benefir for its resistors as the resistors in TDP1603 i.e. produced out of same batch of resistive material. It may then mean that TC for each resistor is not too great, but they all have same TC. Problem with mouting PCBs with resistors is that the resistors come from all different batched with different TC. Individual temp scan of the resistors would help here.

Just an idea...

Using a resistor array on the NU180 was suggested by Kleinstein at very beginning. Since the design of the 3458A uses a non-standard 80 kΩ resistor value, we have to opt for the suitable standard value— a 100 kΩ res array.This requires making a series of adaptive adjustments on the A3 board to implement it, which itself becomes a barrier—peoples (like me) are reluctant to make so many modifications to their A3 boards.

The reason I chose six metal foil(4 80K, 2 100K) through-hole resistors for this PCB revision is that I found and purchased some 80 kΩ and 100 kΩ salvaged components on taobao at a very low price (about $1 per piece). Simple tests showed that the TCR of individual resistors is very low, potentially well below 2 ppm/K. So I gave it a try, and the results so far are acceptable. The performance could likely be further improved by screening for TCR trend matching, I agree with that point.

[Kleinstein]

If taking use of 100 kΩ OSOP or TDP1603 resistor array on NU180, the required changes would be:

On the A3 board, change R168 from 10.2K to 19 kΩ(reason see below).

On the A3 board, change R154 from 604 kΩ to 755 kΩ.

In the ZGJC section, change R185 from 3.01 MΩ to 3.76 MΩ.

Change R161/R167 from 301 Ω to 100 Ω.

If using input supply modulation, change R176 from 24.3 kΩ to 30 kΩ.

As for boosting 7.1 V to 15V, using an LT5400‑8 (9 kΩ/1 kΩ/1 kΩ/9 kΩ) configured as 9 kΩ : 19 kΩ is feasible.
The +vref 5 V could be fulfilled by an LT5400‑1 configured as 30 kΩ : 10 kΩ.
For the +15 V to -15 V conversion, an LT5400‑1 could still be OK.

These are indeed quite a few changes. Are there any others that need to be considered?

The Changes to R161/R167 may not be needed. The output range of the LT1001 may still be OK.
The Change to R168 could be from an extra resistor on the U180 replacement.
Chances are the change of R185 in the zero jump circuit is not absolutely needed.
Ideally one would also change R172 or R173 a little, as changing R176 would also change the gain. The alternative would be adding a resistor from U171 pin 8 to ground, to have again the 24.3 K impedance for R176.
The change is relatively small and one may get away without it - this is especially with low R_on switches that may not need the supply modulation at all.

I agree that this are some additional changes to the A3 board.

[MiDi]

The constant -2µV offset for negative voltages is strange, how do you calculate the INL, could you provide the raw measurements?
Could you please give some detail on noise level, the used settings and duration of observation?

The INL calculation is based on using measurements from U180 as the reference. The difference between NU180 and U180 measurements from 0V AND +10V is used as the basis for gain calibration. Then, all voltage measurement points from -10V to +10V of NU180 are adjusted accordingly by the gian. After adjustment, these values are compared with U180's measurements to calculate the INL. Zero-offset alignment should also be performed, but since the offset difference at zero is pretty small, this step was omitted. The raw data and calculations are in the attached spreadsheet. Hopefully this data won't cause too much confusion.

The noise test followed the method previously suggested by Kleinstein: with the input short-circuited, voltage readings were collected at 1 PLC, 10 PLC, and 100 PLC（All in 10V range）. Data was received by using a Keysight 82357B GPIB adapter and RMS was calculated in real-time on DMM_tool. Each measurement consisted of 100 data points. Of course, this measurement includes the noise from the A1 board as well, but it can still serve as a comparative reference for evaluating the noise level.

INL calculation is solid. Are the values from each unit taken at the same time (synchronous)? A second INL test would rule out a fluke.

The noise is similar to my unmodified unit:
NPLC MiDi wanghar (ACRMS in µV)
Edit: changed to 1 NPLC for MiDi as the unit has elevated noise for >1 NPLC
  1 0.68 0.88
 10 0.22 0.42 (MiDi calculated from 1 NPLC: 0.68/10^0.5)
100 0.07 0.13 (MiDi calculated from 1 NPLC: 0.68/100^0.5)

Calculated values of 10s intervals of multiple hour measurements (replace , with .):
1 NPLC:
Vpp mean   3,9E-6
Vpp std   413,0E-9
Vpp min   2,8E-6
Vpp max   5,7E-6
Vacrms mean   678,1E-9
Vacrms std   32,9E-9
Vacrms min   570,7E-9
Vacrms max   821,1E-9
Vpp mean/Vacrms mean   5,76

10 NPLC:
Vpp mean   1,6E-6
Vpp std   284,5E-9
Vpp min   265,0E-9
Vpp max   2,9E-6
Vacrms mean   383,3E-9
Vacrms std   57,7E-9
Vacrms min   115,9E-9
Vacrms max   645,7E-9
Vpp mean/Vacrms mean   4,08

[wanghar]

INL calculation is solid. Are the values from each unit taken at the same time (synchronous)? A second INL test would rule out a fluke.

To ensure synchronous readings, the INL test was repeated. Both units transmitted data simultaneously to the DMM_tool app via GPIB adapters. All data was imported into a spreadsheet, with each voltage point averaged over 10 measurements, and then the INL was calculated. Before testing, both units underwent ACAL. This measurement result offers a higher confidence level.  The result is not bad.

Regarding noise testing, on my original U180 unit, I measured RMS noise of 0.66 µV at 1 PLC, 0.27 µV at 10 PLC, and 0.07 µV at 100 PLC with the input shorted, which is close to your results. The noise on the NU180 is still considerably higher compared to the U180.

[cdlg]

INL calculation is solid. Are the values from each unit taken at the same time (synchronous)? A second INL test would rule out a fluke.

To ensure synchronous readings, the INL test was repeated. Both units transmitted data simultaneously to the DMM_tool app via GPIB adapters. All data was imported into a spreadsheet, with each voltage point averaged over 10 measurements, and then the INL was calculated. Before testing, both units underwent ACAL. This measurement result offers a higher confidence level.  The result is not bad.

Regarding noise testing, on my original U180 unit, I measured RMS noise of 0.66 µV at 1 PLC, 0.27 µV at 10 PLC, and 0.07 µV at 100 PLC with the input shorted, which is close to your results. The noise on the NU180 is still considerably higher compared to the U180.

Hi 王, 了不起，如此漂亮的数据令人振奋，请求转让一块空板加入测试，权限原因我无法私信给你，盼复。

[voltsandjolts]

Hi 王, 了不起，如此漂亮的数据令人振奋，请求转让一块空板加入测试，权限原因我无法私信给你，盼复。

Translation:
Hi Wang, that's amazing! Such impressive data is truly inspiring. I'd like to request a spare board for testing, but due to access restrictions, I can't send you a private message. Looking forward to your reply.