Author Topic: My PSU design ripple and noise with picture measurements  (Read 41078 times)

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Offline Mechatrommer

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Re: My PSU design ripple and noise with picture measurements
« Reply #225 on: November 16, 2022, 09:55:09 pm »
those are in parallel... I remember reading that in parallel does provide benefit of sharing the load for sure, but in our case the load is fine for one inductor. it is just the ripple performance that we need.
yes they share load but reduce inductance just like parallel resistors. reduced inductance than recommended means increased current/voltage ripples and also make converter works harder (hotter).

in your design you seem to use a very generic and low quality IC, having 60mv could be a good result.
ditto! before the era of mVpp smps... but they are few cents ICs..
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Offline Vovk_Z

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Re: My PSU design ripple and noise with picture measurements
« Reply #226 on: November 17, 2022, 10:11:55 pm »
To TS: I guess you want 10-22 uH main inductor. It depends on a datasheet of cause. My guess goes from some 'average' DC-DC convertor IC design.
You dont have to go too far from datasheet value.

Linear post-regulator will improve ripple too (about 10x). Some LDO should do.
« Last Edit: November 17, 2022, 10:13:57 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #227 on: November 18, 2022, 10:09:50 am »
Quote
To TS: I guess you want 10-22 uH main inductor. It depends on a datasheet of cause. My guess goes from some 'average' DC-DC convertor IC design.
You dont have to go too far from datasheet value.

when I return to lab in 4 days I will try putting 2 10uH in series to form 20uH, on a perf board and hooked in the place of 4.7uH one. we'll see. 22uH seems realistic but TI keep telling me it might cause instability. output caps too.


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Linear post-regulator will improve ripple too (about 10x). Some LDO should do.

that is a valid choice too but unless I go for expensive stuff, I would need to use a normal LDO which has some edge of dropout... then I would need a heatsink. this is what I didn't want to begin with but I will see if it is a valid choice.

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Re: My PSU design ripple and noise with picture measurements
« Reply #228 on: November 18, 2022, 12:20:18 pm »
speaking of LDOs, I found this: https://www.ti.com/product/LP38503-ADJ

exact part number is LP38503ATJ-ADJ/NOPB which has thermal junction to ambient of 33 degrees and junction to case of 22 degrees which I think very good. not cheap by any means but still can make it.

if this choice was taken, then I can get local aluminum sheets cut to specific size to be fitted on top of both regulators... any Aluminum sheet heatsink can do such low requirements. I need this heatsink to be dirt cheap, so no buying and shipping!

meaning 0.55 maximum dropout * 3 amps = 1.65 -> 1.65 watts * 22 = 36.3 degrees + 25 for ambient = approximately 60~65 degrees total. any heatsink can do it right?

if paired with switcher IC which can deliver relatively clean signal, then i think we can make it to <10 mv p-p under full load right? current switcher is dual output which is fantastic but needs more tweaking to get better noise output.

looking forward to your opinions.


this creates another issue which is how to stick the aluminum heatsink to both of them? I see such products use thermal adhesive but i don't know any good brand or the cost.

Offline Mechatrommer

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Re: My PSU design ripple and noise with picture measurements
« Reply #229 on: November 18, 2022, 12:28:21 pm »
since you are not happy with 5V rail, maybe you can only use linear post-regulator on that rail only.. doing homework for you... LM1085 maybe a good choice. 5mVpp load regulation, 1V dropout x 0.5A = 0.5W should be manageable pcb as heatsink. $2.5 in digikey, cheaper in ebay china. who knows that knock off can do 10mVpp? should be good enough if so... ;D

speaking of LDOs, I found this: https://www.ti.com/product/LP38503-ADJ
try avoid ADJ version if you are tight on space, that will need more resistors divider. but thats your choice.
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Re: My PSU design ripple and noise with picture measurements
« Reply #230 on: November 18, 2022, 01:17:39 pm »
Quote
since you are not happy with 5V rail, maybe you can only use linear post-regulator on that rail only..

it is for both. I need top performance on 3.3v more than 5v since 3.3v is the main one which powers everything.


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LM1085

I originally thought about this but the high dropout voltage kinda made it not the first choice at least for now.

dropout is 1.5v * 3 amps = 4.5 watts. meaning about 100 degrees, but with heatsink is about 70. very high IMO right?

if i ever go heatsink route i will never get anything from outside... but rather as i said, locally cut from big sheet with nice thickness. after that stuck or glued to the IC.

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try avoid ADJ version if you are tight on space, that will need more resistors divider. but thats your choice.

this particular IC does not have fixed version.. adding 2 resistors is very easy even on tight places so no problem for me.



do you know any thermal glue or anything that can stick the heatsink on the surface of the IC? this is the only way I want to achieve it.

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Re: My PSU design ripple and noise with picture measurements
« Reply #231 on: November 18, 2022, 02:35:49 pm »
Possible other LDOs alternatives:

RTQ2533W -> cheap. PSRR is 60db for lower frequencies at 3 amps but still promise 10uV noise somehow. junction to ambient is 35 degrees. dropout max is 180mv max which is fantastic. so assume 200mv -> total 0.6 watts -> maximum of 20 degrees raise -> 45 degrees total! does this seem too good to be true? 45 degrees (including ambient) does not require heatsink right?  i am worried that it only purchasable from digikey.

its junction to case is worse than junction to ambient, why?

a similar RT9059 available but 450mv dropout max at 3 amps. -->0.45*3= 1.35 watts on vqfn package. 1.35*32.8 c/w = 44.28 == 45 degrees above ambient... +25 = 65 degrees. can this be without heatsink??


MIC35302WD -> cheap but very high dropout which requires heatsink.


MIC37302 -> good overall but 0.5v dropout. however, it states only 5.5 C/W junction to case.

NCV59745AMW180TAG -> not cheap, 100mv dropout typical, 200mv maximum. 0.2*3 = 0.6 watts * 40 c/w = 18 degrees above ambient. this is without case. PSRR seems interesting as the curve displays high value for lower frequencies up to 10khz. I just noticed it cannot output 5v!


MIC68400YML-TR -> expensive, 500mv maximum dropout at 3 amps. psrr less than others. 30 c/w to ambient.



MIC47300WD-TR -> 400mv max dropout.

MIC69302 -> 0.5v dropout, 38 c/w ambient.

ISL80103 -> not expensive, 120mv dropout, but kinda limited availability

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Re: My PSU design ripple and noise with picture measurements
« Reply #232 on: November 20, 2022, 12:34:18 pm »
Hello,

I've been thinking and iterating this design for a while now seeking more options... and I came up with this in the attachments.

key points:

1- using 10uH inductors instead of 4.7u as main switching inductors... as well as using one 10u instead of 33u as main input filter.

2- settle on RTQ2533W as LDO since it ticks all boxes. 200mV dropout will ensure maximum of 0.6 watts for 3.3v 3 amps rail which I think won't need heatsink. if heatsink needed, I can cut 10x25mm aluminum piece and stick it on top of both LDOs.

3- made the design 60mm x 50mm instead of 50x50. this made more room.

4- arranged components to allow the slot, please check it out.

5- switcher now has 22uF 1206 caps, 5 of them instead of 7x10u.


please check for any info or suggestion.

i am still far from lab, need 2 days

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Re: My PSU design ripple and noise with picture measurements
« Reply #233 on: November 20, 2022, 11:09:18 pm »
You're gonna change those FBs (they saturate) to inductors proper (saturate at rated current) right?

Add some R+C or electrolytic footprints to dampen the LC sections.

Add a bypass resistor (optional 0 ohm jumper) to try it without the LDOs first.

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Re: My PSU design ripple and noise with picture measurements
« Reply #234 on: November 21, 2022, 06:50:55 am »
You're gonna change those FBs (they saturate) to inductors proper (saturate at rated current) right?

Tim

here are the ferrite beads: https://www.fair-rite.com/product/sm-beads-differential-mode-2773037447/

the reason to include them was to do some filtering of noise, this particular one can do for lower frequencies. putting inductors will cause drop voltage, and I don't know what value inductor to use. thus, thought that FB was a better choice since its resistance is like 1.2 mOhm.

however, if you mean like small 1uH inductors which have so small DC resistance then yes maybe I can replace the beads seamlessly. LCSC has a collection of such smaller and high current L.

quick edit: hmmm since i won't use the switcher as final stage, then I can afford some dropout since it will already have 200mv max dropout before the LDO. actually, the LDO says 180mV as max dropout at full load so assuming 5mR inductor at 3 amps will have 45mv dropout. so maybe I can just put 250mv total dropout and be safe... or just rely on 200mv total since the rated LDO dropout is 110mv. what do you think?

assuming maximum dropout of 270mV, it will result in 0.81 watts at LDO which makes about 30 degrees temperature increase over ambient = about 55-60 degrees total which I think requires a heatsink. always wanted to get away without one  |O

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Add some R+C or electrolytic footprints to dampen the LC sections.

where exactly? at which stage?

if at LDO stage which has 5x 22u ceramics... is it ok to add another 22u ceramic in series with say 100R resistor as a damper instead of an elec. cap? or better yet 1uF cap with 100R or so? since I do have 1uF in design and it is small and won't take space.

elec cap will be huge capacitance value which will affect the stability of the switcher, or so TI recommended. I am already exceeding maximum allowed capacitance of 68u.


Quote
Add a bypass resistor (optional 0 ohm jumper) to try it without the LDOs first.

at the output of switchers? I can add a load resistor, say 1k ohm to ground.

if 0 resistor is used, then it will be like a connecting bridge between switchers output and LDO stage. is this what you want?



On another point, do you find this layout good? knowing that i am simply adding footprints and so on, not a real design yet but just a rough layout.

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Re: My PSU design ripple and noise with picture measurements
« Reply #235 on: November 21, 2022, 08:52:13 am »
here are the ferrite beads: https://www.fair-rite.com/product/sm-beads-differential-mode-2773037447/

the reason to include them was to do some filtering of noise, this particular one can do for lower frequencies. putting inductors will cause drop voltage, and I don't know what value inductor to use. thus, thought that FB was a better choice since its resistance is like 1.2 mOhm.

You can get inductors like that you know...

Look at the impedance curve.  See the 1A curve.  See how it's so depressed?  How much filtering value do you think you're getting in that condition?

Better yet, don't think -- calculate!  What is the attenuation for such impedance at 1A and 1MHz?  10MHz?  (Bonus points: include capacitor ESR and ESL too!)

(That we should be so fortunate as to be able to model and predict everything we do in EE.  Not always easily enough to be worth doing, but in principle at least.  But this case happens to be one of the easiest to model.)


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where exactly? at which stage?

Yes.  (Inclusive-or.  All of them, most likely.)


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if at LDO stage which has 5x 22u ceramics... is it ok to add another 22u ceramic in series with say 100R resistor as a damper instead of an elec. cap? or better yet 1uF cap with 100R or so? since I do have 1uF in design and it is small and won't take space.

What the heck will 100R do?

...And how would one figure it out?

R = sqrt(L/C), for C being total capacitance (may be the series equivalent of caps on either side of the inductor in question), and L the inductor between it.  Cbulk >= 3C.

You propose R = 100 ohm and Cbulk = C/5.  Even at best, with L(FB) being, let's see, about 40 ohms at 1MHz (zero DC bias) or ballpark 6.4uH, and assuming the capacitors don't drop under bias (they certainly will -- check the characteristic sheet), you'll have 5*22 = 110uF, or Zo = sqrt(6.4/110) = 17 ohms.  100R will reduce the ringing moderately, but won't bring it down to zero (well damped, or overdamped).

(Normally, this kind of connection does not give an overdamped condition; much more Cbulk is needed to get there.  Somewhere around slightly underdamped to critically damped will do fine, anyway.)

Inverting the capacitor counts is more likely to be helpful.  Say just one or two 22uF in parallel, then an R+C using 3-4 in parallel, plus whatever resistance is appropriate.

The fact that Zo is so high, has substantial implications for the load step response.  This impedance has physical meaning.  It represents the peak change in voltage, from a step change in load current.  If you want 10% regulation at 3.3V, for a step change of say the full 2 or 3A load (whatever it was?), that's 0.33V/3A = 0.1 ohm.  Evidently for C = 110uF you need L < 1.1uH.  But for C being smaller as described above, L will be smaller still.

You can measure all of these quantities with a suitable setup.

I don't know how many ways I can emphasize this, by the way.

You can, physically, practically, in a couple of minutes, set up a test to measure all of these parameters.  Impedance, time constant, step response, output DC resistance.

You can do it with an automatic pulse generator, like a 555 into a MOSFET and resistor.

You can do it with a resistor and a wire in your goddamn hand -- you have a DSO more than capable of capturing single events.  You can touch a wire, get the single capture, and inspect the waveform at your leisure!  Very handy indeed.

Anyway.

To do that RC with fewer components, an electrolytic will have about the right ESR, or can be chosen nearby at least.  So, 0.1 ohm ESR, 0.1 ohm Zo, and the output doesn't do any ringing, no nasty step response shenanigans, nice and solid.

Matter of fact, go ahead and do the all-ceramic thing.  Set yourself up for another mess of waveforms.  Do the tests.  See them ring.  See the steps.

Then glom on a big fatty sloppy ESR-y electrolytic.

See it all go "thud".

See it fix all the ringing.

Tweak some other component values.  Goob in a smaller inductor.

Then see what the step response does.

You can do all of this so so easily.

I don't know what I possibly have to tell you to get you to do this.

It's so painfully easy and pleasant to do.

You just have to be willing to grab a few damn resistors and sit down at the scope.

And zoom your scope in once in a while.

What time constant is this all happening at, by the way?

We know this, precisely, as well!

The LC time constant is pi sqrt(L C)/2.  The RC or L/R time constant is, well, exactly those.  Any of those pairs of variables will get you something of interest.


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elec cap will be huge capacitance value which will affect the stability of the switcher, or so TI recommended. I am already exceeding maximum allowed capacitance of 68u.

You don't seem to be too concerned about that given the other poster suggesting you exceed the recommended inductance value as well...


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Add a bypass resistor (optional 0 ohm jumper) to try it without the LDOs first.

at the output of switchers? I can add a load resistor, say 1k ohm to ground.

if 0 resistor is used, then it will be like a connecting bridge between switchers output and LDO stage. is this what you want?

Bypass, as in, to short from SMPS output to LDO output, with LDO removed (DNP = do not place).  To pass it by.  By-pass it, as it were.

Or you can jumper over it with a stupid bodge wire, that's fine too, but as long as you're going to the trouble of making another board, why not make it easy on yourself? :)


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On another point, do you find this layout good? knowing that i am simply adding footprints and so on, not a real design yet but just a rough layout.

The placement should be a significant improvement.  I would not bother with the LDOs at all.

Mind, it's still not clear how much of any of this actually matters, because even just your waveforms and testing are woefully insufficient.  Some combination of these mechanisms (filtering, LDO, CM) will have effect at some point, but how much of one kind of filtering you need to employ before the other comes to dominate, isn't clear.


Somewhat aside, the LDO idea itself is bothersome:

So many people say "just add postreg to clean it up!!", completely ignorant of:
- LDOs have shite PSRR in general, particularly at modest to high frequencies (>10kHz), and at low Vin-Vout (with some standout exceptions);
- A better differential filter and higher Fsw is cheaper and more efficient;
- An LDO does fuck all for common mode noise, which can't be helped by ANY amount of differential filtering.  CM is dominated by layout alone, and some use of CMC, but also more layout.

I think the idea of a postreg mainly persists (i.e. it meets the definition of a meme) because:
1. It's just complicated enough for one to feel proud of building/designing, while still being easy enough to succeed;
2. It sounds good / has a believable function (but as mentioned above, it need not actually succeed at that goal!!),
3. People see a lot of others doing it so it must be good right??!?
3a. ...Nevermind *who* they see doing it.  Or not doing it:

Few professionals use postregs (read: very often, or at all).   And for the occasions that that additional filtering really is well and truly necessary, and where burning that little voltage overhead really is worthwhile (e.g. smaller than the DM filter components), not just any damn LDO will be used, but a type with especially good PSRR (some are in fact available, targeting RF equipment for example), or a discrete circuit such as a "capacitor follower" (taking advantage of BJT characteristics to get exceptional performance).

4. And most especially of all: nevermind if they know they need it in the first place -- or can verify (or have any way to verify!) that it's doing ANY of the claims set out in whatever they saw that inspired them to build it!

Few professionals likewise use them, because there just isn't any damn point to it.  I regularly measure single digit mV output ripple on point-of-load converters, running typical things, you know, an MCU, a few interfaces and peripherals (amplifiers, RS-485 transceivers, etc., you know, the usual add-on junk).

For something like your load with large and frequent fluctuations (variable CPU and GPU activity during a frame, and between frames), 10s of mV would seem normal, and perfectly acceptable.  I have no idea what that system actually specifies (you'd have to see their internal design documents, or at least the data of everything that's running from those direct rails), but I would be shocked if it even cares about 100s of mV.  Perhaps some random glitches would start to occur at that level, who knows.

And then, anything less than that [some 10s of mV], it... simply doesn't matter.  It's meaningless.  It provides no performance or reliability improvement.  It's an internal connection (at least, I assume this connector and cable is short and internal?), it likely doesn't affect EMC.  (Emissions up the power-input cable may be relevant, which will be affected by emissions on the output connector, by the principle of reaction ("..equal and opposite force..").  But no further than that.)

As for just getting it low for, shall we say, academic purposes -- well, now we're measuring something.  So get to measuring.  Do the step load tests, see the transient response.  Zoom in and see the switching ripple.  Zoom in further and see the CM noise.

Can even set up a LISN and measure emissions.  Wire up a ground plane with a few bias tees dotted around, wire up the connectors, and see what noise is present on each one.  Can be used as an introduction to RF theory and EMC testing too.  Lots of academic value we can explore around a humble power supply.

Tim
« Last Edit: November 21, 2022, 08:55:59 am by T3sl4co1l »
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Re: My PSU design ripple and noise with picture measurements
« Reply #236 on: November 21, 2022, 10:17:40 am »
Quote
Look at the impedance curve.  See the 1A curve.  See how it's so depressed?  How much filtering value do you think you're getting in that condition?

aha, so at my 3 amps it won't do much if any, therefore this bead is only suitable for lower power consumption circuits right?

thus, we need to get an inductor which is rated at say 4-5 amps with saturation current more that this, but still has relatively low resistance.

the inductor won't be saturated if choose one more than 5 amps.


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You propose R = 100 ohm and Cbulk = C/5.  Even at best, with L(FB) being, let's see, about 40 ohms at 1MHz (zero DC bias) or ballpark 6.4uH, and assuming the capacitors don't drop under bias (they certainly will -- check the characteristic sheet), you'll have 5*22 = 110uF, or Zo = sqrt(6.4/110) = 17 ohms.  100R will reduce the ringing moderately, but won't bring it down to zero (well damped, or overdamped).

if we go with this, we have 17 ohms as our impedance.

how did you conclude that 100R will not be enough using these calculations?

Z=sqrt(L/C)

assume C=110, for Z to be 0.1 ohms we need L=1.1uH so 1uH is suitable.

if we added another 220u elec, for z to be 0.1R we need L=3.3uH, correct?

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where exactly? at which stage?

Yes.  (Inclusive-or.  All of them, most likely.)

well, putting elec cap as a simple solution will be ok for me except for the maximum capacitance we talked about. yes i exceeded it but not by much, having 5x22 = 110uF caps instead of 68u is kinda accepted but if i have to put 330uf don't you think it is too much?

they recommend low esr ceramics for switcher operation to be fast and so on...

if you were to design this stage of filtering what would you put?

if we go elec. route, meaning just put the elec. cap without a resistance in series right? or should we?

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You can do it with a resistor and a wire in your goddamn hand -- you have a DSO more than capable of capturing single events.  You can touch a wire, get the single capture, and inspect the waveform at your leisure!  Very handy indeed.

I do have a switch to the whole thing. I can hook the scope to the final 3.3v rail, then power on the system with scope at single shot mode to see the step it takes from off to fully on. is that what you suggested? here no need for resistor. unless you mean hook-touch the resistor-wire to another point in the design.

or you actually mean I disconnect the psu from dreamcast and power it, then use different resistors to see the response? like 1 ohm resistor for 3.3 amps or 1.1 resistor for 3 amps. put scope into single shot mode, then wire the wire-resistor to ground then touch 3.3v rail and see what happens?

I need to know what setup you mean exactly and will do it tonight for sure. so please state it.

I can then as you said save the waveform and measure + zoom to stuff.

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You don't seem to be too concerned about that given the other poster suggesting you exceed the recommended inductance value as well...

we were speaking about the inductor, which I will test a 10u instead of 4.7u. however, I already put 110u capacitance instead of 68u. in your experience, does it really hurt going much more? i mean, using elec. cap will surely be a lot.. like 220u at least.

actually, i once soldered a 220u elec cap to the first stage (in parallel with ceramics) and it didn't do damage but still didn't enhance the system performance.

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Bypass, as in, to short from SMPS output to LDO output, with LDO removed (DNP = do not place).  To pass it by.  By-pass it, as it were.

Or you can jumper over it with a stupid bodge wire, that's fine too, but as long as you're going to the trouble of making another board, why not make it easy on yourself? :)

then i would need the ldo to be not installed as you mentioned. installing it myself later on will be hard for me. it is VQFN-20 pins 3.5x3.5mm... very small. I only have soldering iron and some thin solder. will get more stuff like hot air later on but certainly not now.

so maybe having the ldo installed is a good choice for this matter.


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The placement should be a significant improvement.  I would not bother with the LDOs at all.

RTQ2533W LDO seem good and cheap enough, so any improvement they provide is nice and will be easy. i have put 3x22u on LDO input, and 5x22uF at LDO output.

I guess for our damping we need to be concerned with 5x22u of first stage switcher filters + small inductor which replaces ferrite bead + 3x22u ceramic caps at LDO input. anything else I missed?

and I asked a question but no one seemed to notice: if putting 220u elec cap with say 1k ohm in series while both in parallel with other caps, will the 220u be counted with the filtering caps themselves? I mean, would it do good for filtering or just for damping purposes?

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For something like your load with large and frequent fluctuations (variable CPU and GPU activity during a frame, and between frames), 10s of mV would seem normal, and perfectly acceptable.

you could say that. other psus already have "just working fine" to their marketing and I was happy using them.

however, originally, i wanted to achieve like premium quality or let's say a perfectionist approach to product design. maybe i look silly saying it but this is something i like. therefore, i thought nothing is bad if i designed my own solution which delivers very low noise and ripple at full load despite all these frequent simps of power. less noise and ripple is always better, despite sometimes some noise is ok.

original psu 20 years ago was fly-back design, if you dig in previous posts here you may find its output waveforms.

besides the perfectionist stuff, yes, i want to learn how to actually design good stuff. the problem is that patience is not my best feature and wanted to go to market fast since this project got changed a lot and took much time...etc.

_______

ok

action plan:

you kindly specify exactly what and where should i do the resistor-wire measurement as proposed above.

I will do these measurements and report back with nice waveforms. then we analyze them to figure out what to do.

analysis needed: calculate output impedance, figure out L needed in order for Z to be 0.1R, then see which resistor and capacitors value we need.



best regards and always thanks for all this. no scope can measure how appreciated i am.

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Re: My PSU design ripple and noise with picture measurements
« Reply #237 on: November 21, 2022, 10:35:57 am »
As these specific questions with values of capacitance/resistance/inductance come up, it simply sounds like you're missing the point of engineering: a high dimensional problem, a designer can change just about any parameter/value but other things would have to change too.

TI provide all the information needed to simulate the design, then you can quickly try the results of varying different component values. But it seems like you aren't taking that engineering design approach, and are reliant on others to do that work for you. Just using off the shelf design guides will lead to the performance that any other person could do, low barrier to entry, no advantage over competitors. To have a unique product that surpasses the competition the designer needs to add something (effort or special knowledge).
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #238 on: November 21, 2022, 11:24:51 am »
As these specific questions with values of capacitance/resistance/inductance come up, it simply sounds like you're missing the point of engineering: a high dimensional problem, a designer can change just about any parameter/value but other things would have to change too.

TI provide all the information needed to simulate the design, then you can quickly try the results of varying different component values. But it seems like you aren't taking that engineering design approach, and are reliant on others to do that work for you. Just using off the shelf design guides will lead to the performance that any other person could do, low barrier to entry, no advantage over competitors. To have a unique product that surpasses the competition the designer needs to add something (effort or special knowledge).


actually, i worked with TI support on simulating it and we did. I don't quite remember results but I still have the file somewhere. TI ran it on their PC since it is better than mine, but I can still run it fine. check some of the images attached. as you see, we added every detail about components used to have perfect representation. >> I will post sim file once i return home, now just these 2 snips

However then we talked about how big inductor filter at 2nd stage (my idea) was causing 200mv drop...etc and they directed me to the ferrite bead solution which as we saw here was not correct.

I will re-install PSPICE for TI software and try to re-create everything to test.

I am doing effort but i still need more learning. trying the simulation file maybe a good first step + help of this thread. do you think after doing this I can achieve what I want? or simply unrealistic to get down to <10mv p-p at that periodic full load?

thanks

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Re: My PSU design ripple and noise with picture measurements
« Reply #239 on: November 21, 2022, 12:55:30 pm »
I am doing effort but i still need more learning. trying the simulation file maybe a good first step + help of this thread.
imo at this stage, simulation is useless. you need to rig yourself up with necessary knowledges and skills for psu design, such as resonant freq, Q etc mentioned, so you can make educated guess when you want to make component selection, know what the effect of ESR ESL if it really matters, and know why different valued mlcc have different cut-off/notch frequencies thats why people use different valued caps several decades apart instead of many same value. http://axotron.se/blog/decoupling-primer/ then you should know which part to simulate, your area of interest you want to tackle, or make bode plot on some components, etc etc. knows what happens and its effect on control, ripples and stability if you overshoot the recommended L in dc-dc converter's datasheet. and then your pcb is a part of the equation even yourself (or me to my pcb) wouldnt know.

do you think after doing this I can achieve what I want? or simply unrealistic to get down to <10mv p-p at that periodic full load?
that depends on your skills... read this...
https://caxapa.ru/thumbs/348441/Switchmode_Power_Supply_Handbook_3rd_edi.pdf
https://designers-guide.org/design/bypassing.pdf
https://www.comtest.ro/biblioteca-tehnica/5952-4020-DC-Power-Supply-Handbook.pdf

since you are dealing with pcb (1oz or 0.5oz) layout, impedance and parasitics could be the issue...
CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES
PCB layout guidelines to optimize power supply performance
you can google related topic for more...

and many others reading materials and yotuubes.. and become the master of your own fate... cheers.
« Last Edit: November 21, 2022, 03:04:46 pm by Mechatrommer »
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Re: My PSU design ripple and noise with picture measurements
« Reply #240 on: November 21, 2022, 04:26:34 pm »
where exactly? at which stage?
They mainly help at the output. There is much less need for them (R+C) at the input. (I mean we talk about steady-state pulsations, but not about transients).
« Last Edit: November 21, 2022, 04:32:19 pm by Vovk_Z »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #241 on: November 21, 2022, 09:46:55 pm »
I have added the simulation of the circuit as basic as it is. no parasitic stuff added so you see it delivers about 1.5mv p-p which does not comply with real circuit.

I am doing another simulation after putting all parasitics but speed is 3 instead of 0 since my laptop is very poor core2duo. will post it once it is finished.

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Re: My PSU design ripple and noise with picture measurements
« Reply #242 on: November 21, 2022, 10:02:04 pm »
as you see, we added every detail about components used to have perfect representation. >> I will post sim file once i return home, now just these 2 snips

However then we talked about how big inductor filter at 2nd stage (my idea) was causing 200mv drop...etc and they directed me to the ferrite bead solution which as we saw here was not correct.
Perfect, but not correct. Instead of knowing the problem or finding out what it is you build more PCBs with different architectures, learning little from the process. Simulation will not match reality perfectly but it can get close enough to answer most of the questions you keep posting.

Which is quicker?
Simulating 100 times
or
Building 2 PCBs

Normal engineering practice is to stop when something is not working as expected and test/measure/learn to understand why. Then you only need to fix that, not the 6 new problems created with another guess. But as the incredibly patient T3sl4co1l has brought up many times, you are designing toward a marketing number (p-p noise) without first:
having a specification or model of the load
or
measuring the separate contributions to the noise

This seems to be way beyond your capability, with no evidence of you going back and learning the fundamentals. Damping a resonance or changing the value of an inductor might be one of the very many steps and changes needed to end up where you want, but you need to understand those contributions rather than expecting everyone else to contribute the engineering work. As an example: I've not seen any evidence that damping is needed as this looks like more fundamental issues, but only measurement can confirm that.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #243 on: November 21, 2022, 10:31:17 pm »
as you see, we added every detail about components used to have perfect representation. >> I will post sim file once i return home, now just these 2 snips

However then we talked about how big inductor filter at 2nd stage (my idea) was causing 200mv drop...etc and they directed me to the ferrite bead solution which as we saw here was not correct.
Perfect, but not correct. Instead of knowing the problem or finding out what it is you build more PCBs with different architectures, learning little from the process. Simulation will not match reality perfectly but it can get close enough to answer most of the questions you keep posting.

Which is quicker?
Simulating 100 times
or
Building 2 PCBs

Normal engineering practice is to stop when something is not working as expected and test/measure/learn to understand why. Then you only need to fix that, not the 6 new problems created with another guess. But as the incredibly patient T3sl4co1l has brought up many times, you are designing toward a marketing number (p-p noise) without first:
having a specification or model of the load
or
measuring the separate contributions to the noise

This seems to be way beyond your capability, with no evidence of you going back and learning the fundamentals. Damping a resonance or changing the value of an inductor might be one of the very many steps and changes needed to end up where you want, but you need to understand those contributions rather than expecting everyone else to contribute the engineering work. As an example: I've not seen any evidence that damping is needed as this looks like more fundamental issues, but only measurement can confirm that.

until now I have built maybe more than 5 boards, but right now I want to make improvement before making another board. because i want to base my new board on something, rather than just try stuff, don't you agree?

it was not perfect or so but maybe close as you said.

I have listened to Tim's words but still waiting for him to respond with the test i need to do so i can do it. his suggestion will let us see the step load response. then we can see what to do or put.

this project is above me but I am learning as I go and I really made lots of new gains and info along the way. I also want to learn the engineering stuff more so I can rely less and less on other people's help.

So I will be waiting Tim's comment on the exact test method, and I will do it for sure.

do you have any suggestions? you speak about an issue of fundamentals, so kindly inform me where exactly.


 

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Re: My PSU design ripple and noise with picture measurements
« Reply #244 on: November 21, 2022, 11:12:09 pm »
the inductor won't be saturated if choose one more than 5 amps.

Correct.  Or 3A.  Check the datasheet, it will say how much inductance has dropped by, at the current.  Usually like 20 or 30%.  Which is fine.

Make sure it's rated for DC current as well (thermal limit, usually 40C temp rise).  Your demand for low resistance will probably make this trivial, but check anyway.

To emphasize: there are two current ratings.
One is purely thermal.  It has absolutely nothing to do with the electrical characteristics of the component.  This is the only current rating ferrite beads carry.
The other is saturation, which inductors typically bear.  Ferrite beads, you have to discover through the characteristics (if provided at all).

For example, the bead in question is approx. -30% impedance by 200mA.  Pretty pitiful as an inductor.

But it's also a pretty pitiful inductor in general, since much of that impedance is resistance.  That is, it has a low Q (quality) factor.  Indeed resistance dominates above 2MHz.  This makes it great for damping resonances; but not when significant DC current also flows.

Ferrite beads are most often applied to low current loads when a minor amount of filtering is required (and a whole inductor is unwarranted, and a resistor would still drop too much voltage), or signals from connectors to filter picked-up RFI, or to dampen cable resonances, etc.; external connection stuff.


Quote
if we added another 220u elec, for z to be 0.1R we need L=3.3uH, correct?

No, use the bare (low ESR) capacitance only.  The ESR makes the rest looks like a resistor, at least for middle frequencies (around Fo = 1 / (2 pi sqrt(L C))).

This will still affect the control loop response, and it could be that the loop gain is higher, or phase margin lower, below those frequencies, where the capacitances do apparently add (F << 1 / (2 pi ESR Cbulk)), and you get poorer transient response, or oscillation.  In that case, reduce all values closer to nominal and see how it works.

Most likely the ESR acts to stabilize the loop and the permissible amount of (bulk) capacitance becomes unlimited.  But this would have to be tested.


Quote
if we go elec. route, meaning just put the elec. cap without a resistance in series right? or should we?

The electrolytic has ESR.  Shop for specified ESR.

External resistance would be required if you're using something that doesn't have enough.  Aluminum polymer easily go that low.  Ceramic certainly do.  The electrolytic will be smaller than a fat stack of ceramics.


Quote
I do have a switch to the whole thing. I can hook the scope to the final 3.3v rail, then power on the system with scope at single shot mode to see the step it takes from off to fully on. is that what you suggested? here no need for resistor. unless you mean hook-touch the resistor-wire to another point in the design.

No, that's just power-up transient.  That tells very little about performance (it does, but not enough of it).


Quote
or you actually mean I disconnect the psu from dreamcast and power it, then use different resistors to see the response? like 1 ohm resistor for 3.3 amps or 1.1 resistor for 3 amps. put scope into single shot mode, then wire the wire-resistor to ground then touch 3.3v rail and see what happens?

Yes!

Also test with some idle load, so it's not going from 0-100% each time.  Maybe a 10 ohm always connected, then pulse a 1.2 ohm across it.  Or 2 and 2 ohm (50-100% step).

And take the falling edge (100-50% or etc. load step).  In general, they will not behave the same!  The controller is nonlinear.  The closer together the states are, the more similar their responses will be, but you also want to see what happens when transitioning from, or to, light load conditions, or burst mode.


Quote
we were speaking about the inductor, which I will test a 10u instead of 4.7u. however, I already put 110u capacitance instead of 68u. in your experience, does it really hurt going much more? i mean, using elec. cap will surely be a lot.. like 220u at least.

More is permissible if compensation is adjustable.  Which... I guess I should actually look at the TPS54394 anyway...

...Oh it's a hysteretic control, lol.

Yeah it doesn't give a shit what you hang off it.

I would keep the switching inductor small to keep frequency high, and use a modest amount of capacitance at the output.  See Fig.24:
https://www.ti.com/lit/ds/symlink/tps54394.pdf?ts=1669071182112
Just do that (left side), then tack on another 1uH, then 2 x 22uF || 100uF electrolytic.

It will generate ripple at light load, anything with burst mode will anyway but particularly being hysteretic type, it always will, proportionally.  If you must, this can be smoothed out with an LDO.

The LC filter deals with switching noise, the LDO does not.  Note the datasheet:
https://www.richtek.com/assets/product_file/RTQ2533W/DSQ2533W-02.pdf
indicates a mere ~30dB above 100kHz (page 11), give or take the peak there, and whatever happens above 1MHz.  And that's with an obscene amount of output capacitance: most specify 1-10uF, they're calling for 67!


Quote
then i would need the ldo to be not installed as you mentioned. installing it myself later on will be hard for me. it is VQFN-20 pins 3.5x3.5mm... very small. I only have soldering iron and some thin solder. will get more stuff like hot air later on but certainly not now.

so maybe having the ldo installed is a good choice for this matter.

Oh then add in two more, at input and output of LDO, and disconnect it completely, no problem?


Quote
and I asked a question but no one seemed to notice: if putting 220u elec cap with say 1k ohm in series while both in parallel with other caps, will the 220u be counted with the filtering caps themselves? I mean, would it do good for filtering or just for damping purposes?

What is 1k going to do with respect to the fractional-ohms of capacitors already there?  It's just some load.  1k*220u = 220ms, a time constant so glacial it might as well be a DC load, as far as the control is concerned.

Strictly speaking, it would improve damping -- but by an imperceptible margin.

You should ask the inverse question, too: what if too little ESR?  Then it looks like it's parallel with the low-ESR caps already there, and doesn't dampen as well.

Best damping is achieved for ESR = Zo.


where exactly? at which stage?
They mainly help at the output. There is much less need for them (R+C) at the input. (I mean we talk about steady-state pulsations, but not about transients).

Considering the input already incorporates electrolytics, I felt safe using the [all encompassing] inclusive-OR. ;D

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Bringing a project to life?  Send me a message!
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #245 on: November 21, 2022, 11:31:50 pm »
Hello

I have done the simulation with parasitics and more components like my design:

- capacitors are 10u with 10mR esr, along with 5nH parasitic inductance... dc bias also taken into consideration thus i lowered the values.
- added the same amount of caps in all places like the pcb.

input ripple is measured to be 400mv p-p with 50khz but actual psu used is about 100-200mv with maybe as i remember 300khz switching... output ripple is the same magnitude though, plus voltage regulation is not accurate (not an actual issue on real pcb).


meanwhile, I will be reading more material suggested by mechatromer and other materials... also trying to think for more additions and modifications which I never tried yet.

i am really motivated to do the work so that the next pcb is better than this one.

Quote
Yes!

Also test with some idle load, so it's not going from 0-100% each time.  Maybe a 10 ohm always connected, then pulse a 1.2 ohm across it.  Or 2 and 2 ohm (50-100% step).

And take the falling edge (100-50% or etc. load step).  In general, they will not behave the same!  The controller is nonlinear.  The closer together the states are, the more similar their responses will be, but you also want to see what happens when transitioning from, or to, light load conditions, or burst mode.

I will read and respond to your kind post tomorrow.

however, i am glad i understood this portion xD.

I will invest some time into making these resistor loads beforehand, THEN start doing the measurement. I have small perf boards of different types and shapes, will solder resistors on it and make it as neat and practical as possible.

I guess using regular resistors is fine, no need for big powerful power resistors since it will be 1 second or so... except for the continuous one. I may make a DIY power resistor by putting them in parallel. will post you on it for sure with pics.

good night for now and will report back soon.

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Re: My PSU design ripple and noise with picture measurements
« Reply #246 on: November 22, 2022, 01:50:25 am »
More is permissible if compensation is adjustable.  Which... I guess I should actually look at the TPS54394 anyway...

...Oh it's a hysteretic control, lol.
With fixed internal compensation, hence the datasheet giving rather narrow ranges of L and C values. That control scheme has average models so it is possible to design an external compensation solution, but without that it will easily become unstable.
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #247 on: November 22, 2022, 02:22:04 am »
I can hardly make out any labels on that schematic.  It's crammed into the corner of the sheet, labels are overlapping all over.

What th... why do the inductors all say "L = 4.7u / DCR = 5n", did you mix up which field is which?

Miracle the sim runs at all..!


With fixed internal compensation, hence the datasheet giving rather narrow ranges of L and C values. That control scheme has average models so it is possible to design an external compensation solution, but without that it will easily become unstable.

That would be true if it used an error amp, but the block diagram clearly shows a comparator and no time constants.

Think more along the lines of MC34063 ....but, needless to say, much more advanced, so it actually performs well.

The "adaptive on-time" seems to be more the secret sauce.  Whether that 'adapts' as part of a control loop, I don't know, at least at a glance.  Although there's no indication on the diagram of what that actually means; alas, TI has had poor (inaccurate, or outright disingenuous) diagrams before, and it wouldn't surprise me if that's the case here too.

Tim
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Bringing a project to life?  Send me a message!
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #248 on: November 22, 2022, 04:04:07 am »
With fixed internal compensation, hence the datasheet giving rather narrow ranges of L and C values. That control scheme has average models so it is possible to design an external compensation solution, but without that it will easily become unstable.

That would be true if it used an error amp, but the block diagram clearly shows a comparator and no time constants.

Think more along the lines of MC34063 ....but, needless to say, much more advanced, so it actually performs well.

The "adaptive on-time" seems to be more the secret sauce.  Whether that 'adapts' as part of a control loop, I don't know, at least at a glance.  Although there's no indication on the diagram of what that actually means; alas, TI has had poor (inaccurate, or outright disingenuous) diagrams before, and it wouldn't surprise me if that's the case here too.
Not sure I would trust any vendors simplified block diagrams, even when they claim to show the entire system, unexplainable behaviour shows up in testing (regulators in particular).

If you'd like to lift the rug, TI have some ancillary publications SLVA546, SLVAF11, etc
« Last Edit: November 22, 2022, 07:00:50 am by Someone »
 

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Re: My PSU design ripple and noise with picture measurements
« Reply #249 on: November 22, 2022, 05:37:23 am »
Quote
I can hardly make out any labels on that schematic.  It's crammed into the corner of the sheet, labels are overlapping all over.

weird, the pdf seems to zoom nicely with me.

Quote
What th... why do the inductors all say "L = 4.7u / DCR = 5n", did you mix up which field is which?

all parasitic inductors are 5nH but the outside label is not correct since I copied the inductors from the main L=4.7u, and when modifying it from the model it does not seem to update the outside label.

however, maybe you are correct and i didn't update the correct field, I will check again because maybe i didn't update the fields properly.





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