FNIRSI-1013D "100MHz" tablet oscilloscope

[frenky]

I have also found this:
https://github.com/mmicko/prjtang/blob/master/docs/architecture/bitstream_format.rst

Family : AL3
FRAMES:1075 BYTES_PER_FRAME:257 (2056 bits) BYTES_PER_MEM_FRAME:1152 (9216 bits)



And this:

[frenky]

This pdf seems to contain instructions on programming "AL3A10LG144C7":
https://justanotherelectronicsblog.com/wp-content/uploads/2018/11/TD_User_Guide_V4.2_english.pdf

And it contains this pinout:

[pcprogrammer]

Thanks to _AW and frenky

I looked at the pin out in the datasheet _AW provided a link to, and it matches the Cyclone IV pin out, and with frenky finding the match for the jtag idcode makes it a match.

Not sure if the IDE found here can be used to make designs for it: http://dl.sipeed.com/shareURL/TANG/Premier/IDE

[morris6]

Another extra - ordinary challenge. And polishing your Mandarin(?) language skills.

[pcprogrammer]

The TD_5.0.3_28716_NL_Linux.zip file from http://dl.sipeed.com/shareURL/TANG/Premier/IDE does contain an architecture folder with files for the al3 series, so it looks like it should be possible to make designs with this software for this device.

Also a question if the provided license files cover this.

Have to see what it looks like, or is morris6 his post implying the user interface is in Chinese (Mandarin?)

Edit1: The software on linux is in English and needs to be started with ./td -gui
Edit2: The manual frenky supplied shows that the TD application can convert Quartus projects if the device is pin compatible. Should then be easy enough to get started by converting a simple Quartes design

[morris6]

Edit1: The software on linux is in English and needs to be started with ./td -gui
Edit2: The manual frenky supplied shows that the TD application can convert Quartus projects if the device is pin compatible. Should then be easy enough to get started by converting a simple Quartes design

Let's see if I can find my way in this new environment. And then try to upload to the JTAG. But first have a look at the manual before everything fails.

[morris6]

First experience with TD IDE:

The English manual is for version 4.2, the version downloaded by me was 5.0.3 and there are some differences. Main one is the generate .svf output file is missing as far as I can see.

The .bin file that is generated in a first try-out attempt, to flash the flash, has the same length and structure as the original flash content. So that looks good. Uploading to the actual Flash ROM is for a later day.

Once more, a big thank-you to forum members _AW and frenky for pointing it out.

Edit: You also need to download the Anlogic_20220130.lic file, rename to Anlogic.lic and move it to the lic folder of your TD environment.

[pcprogrammer]

On the site with the TD program zip, there are two older versions. TD1812 is version 4.3 and TD1909 is version 4.6. Maybe these versions still offer the possible missing options, like Quartus conversion.

[pcprogrammer]

Have to share this

How often can you do the same to get to what you need.

Code: [Select]

      pcVar16[10] = (char)uVar10;   //Start on 10mns/div
      set_fpga_trigger_timebase();
      get_short_timebase_data();    //Uses the normal capture system to get the samples and calculate min, max, etc.

      if (pcVar16[0x23] == '\0')    //Trigger channel
      {
        calculate_ch1_min_max_avg();
        iVar12 = DAT_8000278c;          //0x801AC04A   channel 1 buffer 4
      }
      else
      {
        calculate_ch2_min_max_avg();
        iVar12 = DAT_80002788;          //0x801AD7BA   channel 2 buffer 4
      }

      uVar13 = 0;
      puVar20 = (ushort *)(iVar12 + 0x14);
      uVar18 = 0;                       //max value
      uVar19 = uVar5;                   //0x0000FFFF  min value
      iVar11 = iVar4;

      //Determine min and max value
      do
      {
        uVar17 = (uint)*puVar20;   //Active channel sample buffer
        puVar20 = puVar20 + 1;

        if (uVar18 < uVar17)   //Get max
        {
          uVar18 = uVar17;
        }

        if (uVar17 < uVar19)   //Get min
        {
          uVar19 = uVar17;
        }

        iVar11 = iVar11 + -1;
      } while (iVar11 != 0);

      uVar15 = 10;
      uVar17 = uVar18 - uVar19 & 0xffff;                            //vpp
      *(short *)(pcVar16 + 0x26) = (short)(uVar18 + uVar19 >> 1);   //center value for trigger level 50%

This is part of the code to set the time base in the auto set routine. It calls the get_short_timebase_data() function to sample the data. Within this function, depending on the enabled channels,  the functions calculate_ch1_min_max_avg() and calculate_ch2_min_max_avg() are called. And what did the programmer do after the call of this function, based on the current trigger channel, he calls one of these functions again. But that is not it. No we are not going to use the calculated data, we are going to determine them again, but now in our own "walk through the samples" loop.

So the answer is three

I have to say that this auto set function tops the lot in how not to do things.

Still have to check on how they decide which time base setting to use, and how it can be improved upon.

Once that is done I need to fill in the measurements and FFT bit. Rework the picture and waveform view bit and look into improving the signal representation with either select-able averaging or some sinc function.

The story keeps on going

[morris6]

About TD IDE version 4.3:

The Anlogic_20220130.lic file is also valid here, rename to Anlogic.lic and move it to the lic folder of the TD environment.

Quartus project .qpf conversion is possible, however it doesn't recognize Quartus .bdf board file, more or less as expected. It wants one or more HDL's as input. Pin planning is converted to the TD .adc format.

For now working with version 5:

.svf file generation: point 8.6 of the Chinese manual that comes with the package: Tools => Device Chain. After "Add"ing your .bit file an option box appears: Create SVF. On second attempt an "al-devicechain" folder was created in my work directory that contained the resulting .svf. With the .svf creation there is an option to "verify"...!

My setup with OpenOCD and USB-Blaster is failing for now. A pity, no sigar!

[pcprogrammer]

To get the auto set functionality working I did some tests that were not so successful I decided it is time to clean up the code first and then write a more proper auto set function, and also tackle the zero offset calibration.

Leading up to this cleanup I tried one other thing with the new found knowledge of the system. I discovered that the FPGA command 0x0D is for setting the sample rate and allows for lower rates then the 2KSa/s found earlier, so for the 100ms/div and 200ms/div settings I tested with 1000Sa/s and 500Sa/s, and these work. This makes it a bit easier to get a first release of the new firmware done.

Added the two sample rate settings to the menu.

For the sample rates 5KSa/s - 500Sa/s I believe the trigger system is not functioning, because it is not keeping the signal in its place, so have to work on that too. In the original the top and right trigger pointers are not shown when 20ms/div or 50ms/div are selected.

Next couple of day's will go into the cleanup and re-write of the sample functions to allow for easier and better implementation of the calibration and auto set functionality.

The picture shows a 1Hz sine on channel 1 and a 2Hz sine on channel 2 at 1KSa/s and 100ms/div.

[morris6]

About reprogramming the AL3A10 FPGA:

Since I would like to save the original FPGA configuration data in the flash rom, I was looking for another JTAG setup, other than the USB-Blaster that has a very high speed, it is ready in 0.2 seconds..! The TD IDE is using an Anlogic programmer with clock speed selection. The Anlogic Github page has the design:

url=https://github.com/AnlogicInfo/anlogic-usbjtag

And also on the website of Anlogic Google found an AL3A Demo board, schematics and demo projects.

http://www.anlogic.com/down.aspx?Id=14&TypeId=14&fid=t14:14:14

This programmer is based on a STM32F103 chip. However, it doesn't have a level translator for the 2.5 volt programming that the Fnirsi board uses. Next week I will receive a "Blue pill" STM32F103. Thinking of adding a 74LVC125 to the design.

Something is funny about the Anlogic programmer schematic. It looks like they are combining some pins of the MCU to create the TCK,TMS,TDI and TDO signals, also a SPI_CS is going from one pin to another, both schematics show this. It's also visible on the picture of the Demo circuit board. Pins are used with pullup activated..? Or are some resistors "not placed"?

I tried the design on a F103 demo board I had in my junkbox. After installing the Anlogic USB driver, this board was recognized by the TD IDE. But that board contains other stuff on some of the pins. Guess what..? It didn't work. So some patience is needed before I can continue my experiments with a Blue pill instead.

[pcprogrammer]

I have been working on the cleanup and had a version with calibration, 50% trigger and the settings on the SD card instead of the FLASH, to make it more a stand alone firmware, free from the original code, but I'm still not happy with the result.

There is seemingly to much noise in the traces of which I'm not sure if it is actual noise or the difference between the two ADC's not being handled correctly. On the simulator the traces look spot on, so the logic seems to be correct. But simulator is not real hardware

Also looked deeper into the auto set and have ideas on how to improve this. Noticed on the original box that when the input frequency is below ~10Hz (for sure at 1Hz and 5Hz) it fails in getting the sensitivity setting correct. Have to sample at different sample rates to come to a proper sensitivity setting. This makes the process possibly longer, but only if the system is not sure about the readings. By using the frequency of the input signal, which is going to be determined within the sample reading loop, the correct sample rate can be set.

So it keeps being a work in progress

[morris6]

About the AL3A10 FPGA:

Finally some progress. A fresh Blue-Pill board flashed with Anlogic's "Flash.bin" gets recognized by the TD IDE. Connecting this to my improvised JTAG connector with an 74LVC125 level translator in between makes it possible to re-configure the FPGA. Configuration takes a few seconds and is succeeding where my earlier trials with OpenOCD and a USB-Blaster were failing.

To load your .bit file via JTAG in the TD IDE:
- open download function
- click 'refresh' to find your chip
- select your .bit file
- click 'run'

To load an .svf file in the TD IDE:
- open Tools => device chain
- click your target in the chain to detect it
- click 'program svf'
- browse to your svf file
- click 'program'

Comparing this setup to the schematic I found earlier: maybe this was part of a more extensive programmer that contained other functions. The second set of signals is not needed for JTAG. For now this setup is working for me.

Attached a schematic of my setup and, for your convenience a copy of Anlogic's "Flash.bin" (renamed to .txt to be able to post here).

[pcprogrammer]

I did some testing on the calibration stuff. Made a capture of several sample buffers for varying volt per division and DC offset settings and noticed that on my second channel the difference between the two ADC's is bad. At max a difference of 11. For channel 1 this is only 2.

It also varies with the level of the offset. When the offset is on the low limit found in the original software (200) there is no difference. The inputs will be out of range. The same for the upper limit (1500). Changing the sensitivity does not make a big difference. Just a single bit. But over the working range of the DC offset it varies from minimum 6 to maximum 11.

So might have to settle on some average between these limits.

Still need to run some tests on the different sample rates to see what happens then. A bit strange is that it looks like the original code is doing the difference measurement with the DC offset on 200. This is what my version does and that possibly explains why it fails.

Attached pictures are made with a mod of my signal analyzer code. It allows me to step through the different sample buffers with the arrow keys.

Tests like these provide a better insight in the working of the hardware. Some other tests I need to do are to figure out how the trigger point determination works and if it is possible to get proper trigger on the 200ms/div to 20ms/div settings.

[pcprogrammer]

Maybe some of the people interested can do a capture to provide more data. Attached is the package that makes a file on startup.

It creates a 1.8MB file called calibration_data.bin.

Can be copied from the SD card by using the scopes USB connection mode.

The second attachment is the linux program I used to look at the captured data. The calibration_data.bin file needs to be in the same directory. Remove the .txt extensions

The source code for this program will be uploaded to the repository after dinner and the dishes .

[_AW]

"Attached is the package that makes a file on startup."

how to, pls)

[pcprogrammer]

Hi _AW,

first of all welcome to the forum.

The procedure to load the test package onto your scope is described on page 45 and more specific this message: https://www.eevblog.com/forum/testgear/fnirsi-1013d-100mhz-tablet-oscilloscope/msg3807689/#msg3807689

The full set of step is only needed once. When the SD card has been prepared it only takes the umount and the dd command to load a new package. (Steps 7 and 12)

See this message: https://www.eevblog.com/forum/testgear/fnirsi-1013d-100mhz-tablet-oscilloscope/msg3809966/#msg3809966 for more details on how to load and unload after the SD card has been prepared.

Cheers,
Peter

[ded]

Hello pcprogrammer,
thank you for your excellent work.
I read along very interested, but unfortunately can not contribute much.
Therefore, I have now taken the opportunity and provide you with the calibration data.

Unfortunately the evaluation program does not work with me (Ubuntu 20.04).

Code: [Select]

X Error of failed request:  BadMatch (invalid parameter attributes)
  Major opcode of failed request:  73 (X_GetImage)
  Serial number of failed request:  20
  Current serial number in output stream:  20

Greetings ded

[pcprogrammer]

Hi ded,

welcome on the forum, and thanks for the uploading the data.

The error message the program on ubuntu gave probably has to do with the size of the display. I'm working on a system with two 2560x1440 displays and when I try to use X_GetImage with sizes that are bigger then a single display I get the same error.

I will check the data you provided.

Thanks,
Peter

Edit: Yours is not as bad as mine. The second channel is also worse then the first, but the max I noticed is -7 and min -5. Channel 1 has 3 and 1.

[_AW]

Hi pcprogrammer. Thank you!

[pcprogrammer]

Hi _AW,

thanks for the data. And with this we have a winner

Your scope has the touch panel with the extra scan lines. So your flash backup can give some insight what is done there.

The calibration data of your scope also shows the second channel having a higher difference between the two ADC's, so might this point to a problem in the PCB design.

Min and max for channel 2 are 6 and 13, but the 6 is only near the top. For the wider range the lowest is 10. Channel 1 has -1 to -3.

Thanks again,
Peter

[Alex62]

Hi, my data.

[pcprogrammer]

Hi Alex62,

thanks for the data. Yours is a bit better. Channel 2 also a bigger difference then channel 1, and the latter a bit bigger then the other data so far.

Channel 1 min, max: 3, 6
Channel 2 min, max: 6, 8

Cheers,
Peter

[frenky]

My data is attached.