Programming (non-JTAG) MAX7000 devices

[Rettervondunkel]

Hello, I'm absolutely impressed, thank you for all the time you've invested, Gustavo. I'm an enthusiastic electronics enthusiast and apprentice, I'm 52 years old, and I'm trying to restore a stereo system that has an old 7032 chip installed. I need to be able to access it, erase it, and then reprogram it. I have the programs, I have the .pof file, and now I'm waiting for the components to arrive to build a ByteBlaster-II.
I have an Arduino Mega 2560R3 and an Arduino Nano, and after reading the entire post, I don't know where to start, and I would greatly appreciate your help.

[jgustavoam]

Hi,

I know the blog is confusing. That's why I've archived the most important information on Github. If you have any questions or difficulties, let me know.
Please specify your CPLD model.

https://github.com/Gustavomurta/EPM7032_CPLD

Use this sketch to erase EPM7032SLC44 CPLD.
EPM7032S_programmer_ERASE_V10.ino

and this schematic:
EPM7032S PARALLEL PROGRAMMER GUSTAVO 2025.JPG

[Rettervondunkel]

Fantastic, I'll download it and check it out now.
It's a pleasure, and thank you very much.

[jgustavoam]

Please specify your CPLD model.
Everything that is marked on the chip

[Rettervondunkel]

How do I proceed? How does the Arduino communicate with it? Does the Altera software recognize the Arduino as an interface?

[jgustavoam]

Unfortunately, our project doesn't work for your chip type yet.
It only works for chips with S - EPM7032SLC44.

Do you have a programmer that can be used to program your EPM7032LC44 chip?
Your chip doesn't work with Byte Blaster.

[Rettervondunkel]

I have USB Blaster, Latticce, Willem Programmer, Xprog, and Arduino. Which one do you need exactly?

[jgustavoam]

Is it possible to replace your EPM7032LC44 with an EPM7032SLC44 (JTAG)?
If so, you could try unlocking the CPLD with an 'S' and using it on your board.
Do you have the programming code for your CPLD?

If you recompile the project for the EPM7032S device in a compatible Quartus, the project usually migrates without difficulty.
The EPM7032S has extra features, but it continues to support the logic of the original EPM7032.

[Rettervondunkel]

Yes, I ordered one with an S, it should arrive any minute now. When it arrives, along with the components to make the ByteBlaster, how do I proceed?

[Rettervondunkel]

Yes, I have the code and I also have this Atmel

[jgustavoam]

I'm not a CPLD expert, but I think recompiling the project for the EPM7032S CPLD should work.

Try programming the EP7032S with Byte Blaster. If you can't, your chip is probably locked.
In that case, use our project to unlock it before reprogramming.

Our project was developed and tested for Altera CPLDs only (not ATMEL).

[Rettervondunkel]

I'll wait until the Altera arrives, that way there won't be any mistakes.

[ukamak]

The thread title is "How to program an EP7032." Currently, there's no information on how to do it; we've basically focused on being able to reset EP7032s, EP7064s, and EP7128s so we can program them via JTAG.
As jgustavoam says, the best solution would be to replace the EP7032 with an EP7032s, so you could program it via JTAG without needing a more expensive programmer. Alternatively, someone could program the EP7032 for you; if you have the source code for what needs to be programmed, I could help.

[Rettervondunkel]

The electronic components have arrived, now I'm assembling the Byteblaster 2, and then I have to burn the file onto the CPLD.
Exactly what is the procedure?
How do I do it? With the Arduino?

[ukamak]

To use a parallel byteblaster 2 You will need
- windowsXP
- maxII plus software , you can found on "https://archive.org" , search "2002_altera_max_plus_ii_1023"
- Install drivers from some quartus installation. 
    > bblpt.exe /i

EP7032 don't support jtag , you need a programer like labtool48xp
EP7032S support jtag, you can program with altera maxxII plus

You can have problems if your altera code use the jtag pins for I/O's , after you can't read or erase it anymore, for that we use the arduino , to erase it and recover the jtag port.
Also You have USBblaster , that works with usb port and quartus software that can be run in win10

Do You have the sources or code to program Your device? , we can try to write it to EP7032 and EP7032s and see if it uses jtag pins

Also if you have the pof file for EP7032 and You wnat to use it on EP7032s You need to convert it , the file don't work directly.

[Rettervondunkel]

Good afternoon.
I have the Max II Plus software, a laptop with XP, and a parallel port so I can use other EPROM programmers.
Which drivers are you referring to? I've ruled out programming or reading the EP7032 due to resource limitations.
How can I tell if the code in my .POF file is compatible with JTAG?
I have several Arduino models. How do you get the Arduino to detect, read, and program them?

I also have a laptop with Windows 10 in addition to the ones I have with XP, and two different USB Blaster models, as well as several versions of Quartus software.

I have the original .POF file, which a friend gave me, extracted from an EP7032. From what you've said, I need to convert it to EP7032s format; otherwise, it won't work. How do I do that?

Thank you for your help.

[ukamak]

- Port the design to the Atmel/Microchip ATF1502AS and use the POF2JED utility to convert the Quartus-generated .pof into an Atmel .jed
- Labtool 48uxp can do the conversion

- Maybe with quartus also can be done.
 
To use maxII plus and parallel port You need the drivers , You can download from here byteblaster_II_taobao https://1drv.ms/u/c/ad38fc009b3cd085/IQD_HexEgsSXTpswwATod838AdtpyhVvWjNcAHbWe4OyAHQ?e=Hnngs2
Some info here also https://www.intel.com/content/www/us/en/support/programmable/support-resources/download/dri-bb-xp.html

Pof file is diferent for every device, package etc , for this reason need to be converted

[jgustavoam]

I suggest reading these posts.

EPM7032S - Programming with MAX Plus II V9.3:
https://www.eevblog.com/forum/fpga/programming-(non-jtag)-max7000-devices/msg6169817/#msg6169817

EPM7032S tests with Old PC - Quartus 13.0 Sp1 + Byte Blaster LPT1:
https://www.eevblog.com/forum/fpga/programming-(non-jtag)-max7000-devices/msg6168995/#msg6168995
See the attached files for the Byte Blaster project.

[AK6DN]

Good afternoon.
I have the Max II Plus software, a laptop with XP, and a parallel port so I can use other EPROM programmers.
Which drivers are you referring to? I've ruled out programming or reading the EP7032 due to resource limitations.
How can I tell if the code in my .POF file is compatible with JTAG?
I have several Arduino models. How do you get the Arduino to detect, read, and program them?

I also have a laptop with Windows 10 in addition to the ones I have with XP, and two different USB Blaster models, as well as several versions of Quartus software.

I have the original .POF file, which a friend gave me, extracted from an EP7032. From what you've said, I need to convert it to EP7032s format; otherwise, it won't work. How do I do that?

Thank you for your help.

That .pof file is good for the 7032 non jtag device only, and there is no documented way to convert it to a .pof file for a 7032S JTAG device. You need the source code to recompile.
Using Atmel/Microchip POF2JED you can convert the 7032 .pof to a .jed for the ATF1500(A) device, but it is obsolete and a non-JTAG device also.
There is no option using POF2JED to convert your 7032 .pof file to a .jed file for a JTAG programmable device.

Once possibility is, using POF2JED on your 7032, convert it to a .jed for the ATF1500 series device. The jedec file is ascii and human readable, and the format allows
for reverse engineering the logic equations. Atmel/Microchip shows the logic fusemaps for ATF1502/4/8 devices, for example, in their datasheets, so one can (with a lot
of effort) reverse engineer the logic equations for the device. The datasheets I have for the ATF1500 don't show the fusemap in detail, so that may be a issue.

[Rettervondunkel]

Thank you all, you're very kind. After examining each and every option, it seems I have no other choice but to use the regular 7032, since I'm not sure if programming the version with the "S" will work. So I've started looking for a Labtool 48uxp programmer, and I've managed to get one that will arrive this week. We'll see how it goes.

I'm very grateful for your help.

[Beta_vulgaris]

jgustavoam, great!
I expected some similarities between JTAG and parallel modes (it looked logical to reuse as much internal circuitry as possible in such quite small devices) and here is it!

The 237-bit DR of 0x1E instruction is definitely the chained 108+108+21 bit address register corresponding to 3 parallel mode regs with inputs A2, A1, A0 and clock A6.
Looking at your SVF file it seems to be organized this way (right to left): 108 bits A0 (or A1 ?), 21 bits A2, 108 bits A1 (or A0 ?).
In "CHECKING SILICON ID" they shift two 1s into the leftmost position of A0 and A1 regs:
1000000000000000000000000000 00000 800000000000000000000000000 - the middle 21-bit part doesn't fit into 5 nibbles, it's LSB is in the rightmost nibble of the left part (and that's why the left part has an additional nibble 1 with 3 unused bits). This corresponds to pulsing A6 107 times with A[2..0]=000, then pulsing A6 one more time with A[2..0]=011 - setting addresses of A and B halves to 0 (in one-hot encoding - set the 0th bit to 1, all others to 0).
The PROGRAM and VERIFY sections loop through addresses 1-107, moving the "hot" bit in both 108-bit parts from left to right, then loop through addresses 0-20 of the middle part.

The other interesting part is 84210842108421084210 (binary 10000 10000...) pattern in SDINx regs shifted to right between 16-bit SCOx readouts. We had the same in parallel mode, just without full reloads on each step. Unlike JTAG, there is a dedicated SCK clocking SDINx chains, so we just load the initial 10000 10000... pattern and shift it using SCK after each 16 bits of SCOx. Taking into account that MAX7k consists of left and right LABs x 16 macrocells x 5 product terms, my guess is SDINx input bits are activating product term config bits of all 16 macrocells of a single LAB (16x5=80 bits) and SCOx output bits are per-macrocell single bit outputs (16x1 bits). So a full readout procedure looks like this:

Code: [Select]

for (lab=1; lab<108; lab++) //don't read addr 0, that is "fake LAB" with SiliconID
{
    ShiftAddressIn(lab);
    for prod_term=0; prod_term<5; prod_term++)
    {
        ShiftSDINIn( (1<<prod_term) | (1<<prod_term)<<5 | (1<<prod_term)<<(5*2) | ... | (1<<prod_term)<<5*15) );
        data = ShiftSCOOut(); //16 bits
    }
}
and the chip's memory is logically organized as:
- 2 "sides" (left/right on the "EPM7064S Block diagram"), selected by using A or B pins SDINx/SCOx/SDOUTx in parallel mode or by 16/1A, 22/26 JTAG instructions, of
    - up to 108 (depends on device size) LABs, selected by setting a single bit in A/B 108-bit address regs, of
        - 16 macrocells, selected by 5-bit groups in 16x5-bit SDINx regs and single bits in SCOx regs, of
            - 5 product terms, selected by setting a single bit in each 5-bit group of SDINx regs

The part addressed by 21-bit middle (or shifted into A2 in parallel mode) address register needs to be studied more. It's address 0 (LSB set to 1) selects the "security flag" area, the rest is IDK.

New found U.S. Patent 5,650,734 "Programming programmable transistor devices using state machines" from December 1995, Fig. 2 and 9 showed TM, BE, NTPW, and CLRREG! TM for tunnel mode, BE bulk erase, NTPW tunneling pulse width, CLRREG clear register.

[jgustavoam]

Excellent find! I'm going to read it.

Programming programmable transistor devices using state machines
https://scholar.google.com/citations?view_op=view_citation&hl=en&user=J-6FV7EAAAAJ&citation_for_view=J-6FV7EAAAAJ:j3f4tGmQtD8C


You've given me a good idea! We can search through all the patents for additional information. Check the list of patents in the MAX+PLUS II "Getting Started" manual.

When searching with ChatGPT, it provides a brief summary of the patent.

[jgustavoam]

I found it very interesting and relevant. I haven't tested it!

Pico USB Blaster
This firmware turns your Raspberry Pi Pico (or other RP2040/RP2350-based board) into an Altera USB-blaster / Intel FPGA Download Cable-compatible JTAG/AS/PS programmer
usable with Quartus, OpenOCD, etc.

https://github.com/thisiseth/pico-usb-blaster