Might I remind you that we are acquiring error free data
Can you please explain what you mean by "error free data"?
Maybe we misunderstand what you mean by it. As explained previously, there is no such thing as "error free" when measuring physical phenomenon (apart from some rather exceptional circumstances). There is calibration error, quantisation error, and noise. Errors will then accumulate in any derived parameters. Read up on ENOB as mentioned by ogden.
"Garbage in, garbage out" as they say.
so while yes it is only measuring current and voltage, the error free data and calculations allow SDE to receive 24 bit resolution on each of the parameters (i.e. reactive power, phase angle, harmonics, etc.).
Yeah, if you have 24-bit inputs then unless you do your math wrong you can retain 24-bit (math)* resolution (more or less) with the derived parameters.
Your suggestion that we are using a 24 bit ADC chip is also based on the presumption that AD conversion is separate from the data processing, when in fact it is not, it is all done simultaneously on 26 channels for individual parameters. All 26 channels are measured individually on each phase, neutral and ground, not all together.
Um, what?
It was you stating that you're doing 24-bit sampling at MHz rates (it is also in your white paper).
We're happy for you to correct us if we have assumed something wrong, but be professional and give us some facts if you would like to get treated professionally in return.
OK, so what I understand from this response is that you sample the 2 parameters on all circuits in parallel with multiple ADCs, and I assume you then do the calculations for derived parameters "simultaneously" with an FPGA.
As you state there are only two parameters you can actually measure per phase/neutral/ground circuit - i.e. voltage and current. The rest of your 26 derived parameters are going to be calculated from those plus elapsed time.
Just because you may be collecting 26 parameters at a high rate doesn't mean you're sampling at the speed you have constantly implied.
You have demonstrated with your own words that the 6ns sampling interval was nonsense all along.
* edited to add "(math)" - rather unlikely you can calculate derived parameters like PF, phase angle, etc to actual 24 bit resolution (i.e 6+ digits!).