Re: capture data from ADC with ISERDESE not working
Rainwater on 28 May, 2024 16:45 in FPGA
Ahhh. Use code tagsCode: [Select]library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;library UNISIM;use UNISIM.VComponents.all;entity Prueba_ISERDESE is Port ( test_signal : in std_logic; --- seƱal para prueba del ISERDESE i_ADclk_p : in std_logic; i_ADclk_n : in std_logic; i_Lclk_p : in std_logic; i_Lclk_n : in std_logic; i_rst : in std_logic; salida : out std_logic_vector (7 downto 0) ); end Prueba_ISERDESE;architecture Prueba_ISERDESE of Prueba_ISERDESE issignal adclk_i : std_logic;signal lclk_sys : std_logic;signal not_lclk_sys : std_logic;signal Lclk : std_logic;signal Lclk_B : std_logic;signal adclk : std_logic;begin Lclk <= i_Lclk_p; Lclk_B <= i_Lclk_n; process (Lclk) begin if rising_edge(Lclk) then adclk <= i_ADclk_p; end if; end process;------------------------------- bufio_lclk_sys : BUFIO port map (I => Lclk, O => lclk_sys) ;not_lclk_sys <= not(lclk_sys);------------------------------bufr_ad_n : BUFR generic map(BUFR_DIVIDE => "1", SIM_DEVICE => "7SERIES") port map (I => (adclk), CE => '1',O => adclk_i,CLR => '0') ; ------------------------------- iserdes_frame : ISERDESE2 generic map( DATA_WIDTH => 7, --- 7 DATA_RATE => "SDR", SERDES_MODE => "MASTER", --IOBDELAY => "IFD", DYN_CLK_INV_EN => "TRUE", DYN_CLKDIV_INV_EN => "FALSE", INTERFACE_TYPE => "NETWORKING") port map ( D => test_signal, DDLY => '0', CE1 => '1', CE2 => '1', CLK => lclk_sys, CLKB => not_lclk_sys, RST => i_rst, CLKDIV => adclk_i, CLKDIVP => '0', OCLK => '0', OCLKB => '0', DYNCLKSEL => '0', DYNCLKDIVSEL => '0', SHIFTIN1 => '0', SHIFTIN2 => '0', BITSLIP => '0', O => open, Q8 => salida(7), Q7 => salida(6), Q6 => salida(5), Q5 => salida(4), Q4 => salida(3), Q3 => salida(2), Q2 => salida(1), Q1 => salida(0), OFB => '0', SHIFTOUT1 => open, SHIFTOUT2 => open);end Prueba_ISERDESE;