Simon: Wow, what a sharp eye! Yes, that was the problem. Thank you!
About stray capacitance: One comment concerned the ladder resistors. Those are the 5 resistors in a row to the right of the PGA. There's nothing further I can do to reduce capacitance there.
The through-hole vs. surface mount resistor issue does impact stray capacitance. I've set up the wiring so that either footprint can be removed without any other changes being necessary, but significantly more stray reduction would be possible if either is removed outright. I could also go back to merged surface-mount plus through hole footprints, which would save a small amount of capacitance.
A question I have about stray capacitance regarding the 80k resistors is which side, if either, of the resistors is more sensitive to stray capacitance. That is, between the switches and the resistors, or between the resistors and the pins. At the moment, it favors resistors-to-pins, but I suspect that it's the other side that is more sensitive.
Another thing I should check is whether pins 4, 8 and 64 (+12 Ref.) are shorted on the A3 board or not. If they are already shorted, then I can delete a few short traces to all but Pin 4 or 8 (those are about equal).
(No, I'm not going to move the CPLD to the bottom. I do believe it would be better-off there, but it's too difficult to fabricate under most circumstances.)
I'm still hoping to hear an informed opinion about the main clock line (between inverter and the FF).