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Repair / Re: Tektronix SC502 Alt and Chop mode fault
« Last post by BlownUpCapacitor on Today at 04:43:43 am »
Update: It's fixed! Q350 was the issue the whole time! Replaced it with 2N3904 and it works perfectly now!
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Beginners / Re: uCurrent Gold Schematic
« Last post by Kleinstein on Today at 04:39:50 am »
A single LDO is probably OK. It may help to isolate the digital part with  an extra inductor / resistor in the supply part. For the decoupling it is not just the parts and the schematics, but possibly more the layout that is relevant. So keep the fast part local and mind the ground paths (avoid ground coupling).  A 2nd LDO would not help much with the layout - more complicate things.
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Test Equipment / Re: Hacking the Rigol MSO5000 series oscilloscopes
« Last post by Sergey_21 on Today at 04:36:03 am »
Okay, let's go over the moment of correctly installing Python and its modules; if at least one of the modules is not installed,
the script will not be executed at all, but we see that it is launched.

Here is the sequence I followed (according to your instructions):
1) installed firmware version 1.3.2.2
2) python rigol_kg2.py –i  xx.xx.xx.xx
3) python rigol_kg2.py –r xx.xx.xx.xx (we get an error, but the key file is being created)
4) python rigol_kg2.py     xx.xx.xx.xx
5) flash again firmware version 1.3.2.2
6) python rigol_kg2.py –i xx.xx.xx.xx
7) python rigol_kg2.py     xx.xx.xx.xx

Is everything right?




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They now offer a new version of the probe, available in 200, 350 and 500MHz version:

2159935-0
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Metrology / Re: Why don't we see more TDC based high-resolution ADCs?
« Last post by Kleinstein on Today at 04:34:04 am »
A voltage to time conversions would be similar to a dual slope ADC.
A dual slope like ADC is limited in the INL by the dielectric absorbtion of the integrating capacitor. Another point it the noise and using more of the time for actual input integration to get a low noise bandwidth for the input. E.g. the ICL7106 uses only 25% of the time to actually measure the input, while a MS ADC is usually at > 98% for not very fast conversions.
The clock and actual time measurement are not really the critical points in a high resolution integrating ADC.
A simple multislope ADC is actually not that much more complicated than a good dual slope ADC build from seprate parts.

For the not so high resolution / limited INL end there are sigma delta ADC chips and good SAR type ADC chips, that can be pretty affordable (cheaper than a TDC chip).
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Test Equipment / Re: Vevor SDS1104 for first oscilloscope?
« Last post by EvgenyG on Today at 04:31:39 am »
I don't know what the market looks like in Australia, but I have been watching various sites here in the US in hopes of finding a deal on a used Siglent SDS1104XE or Rigol1054DZ. So far, the only things I'm finding are people offering them, used, for prices HIGHER than what I can get them brand new from Amazon. :(

Very similar here in Aus. People ask ~90% price of a new device. I don't know who would buy a 5-10 year old device with no warranty for that kind of money, not me.
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Power/Renewable Energy/EV's / Re: Totem Pole PFC is over-hyped?
« Last post by temperance on Today at 04:31:24 am »
Thanks for your reply. So in short the TI solution doesn't properly. I haven't had time to play around with the Infineon XMC solution. Maybe around summer or so.

Regarding the noise.

I have no idea about your level of experience with developing switching power supplies so I might suggest something you all ready know. If probing around with normal probes when almost no output power is delivered indicates to me that there is something wrong with how the power components are switching. If there is a problem, it is visible when probing the gate wave forms and inspecting the gate source miller plateau voltage at turn on. Any kind of wrinkles or sings of oscillations must be "cured" before you can continue because it will cause common noise all over the place.

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Test Equipment / Re: Vevor SDS1104 for first oscilloscope?
« Last post by tautech on Today at 04:23:27 am »
If the price is right then a used SDS1104XE in good condition would still be worth serious consideration particularly for somebody on a budget. If the OP is not in a desperate rush for a scope then this would be my recommendation, cheaper than new and far superior to what they are currently considering.

I just saw someone buy a second hand SDS1104XE for 540 bucks+postage on aus ebay, so prices are not going down that much. New one is still close to 700 on AppVision. I think the scope market is just too slow in Australia and some people don't know about 800X series. We are still yet to see 800Xs here. Everybody else has them for sale but not Australia (and our friends across the ditch). Perhaps wait until the end of financial year to get better deals.
Got ours today.
Real busy contacting those that have patiently been waiting.....
Already need to order more.....  :scared:
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Test Equipment / Re: Vevor SDS1104 for first oscilloscope?
« Last post by EvgenyG on Today at 04:14:07 am »
If the price is right then a used SDS1104XE in good condition would still be worth serious consideration particularly for somebody on a budget. If the OP is not in a desperate rush for a scope then this would be my recommendation, cheaper than new and far superior to what they are currently considering.

I just saw someone buy a second hand SDS1104XE for 540 bucks+postage on aus ebay, so prices are not going down that much. New one is still close to 700 on AppVision. I think the scope market is just too slow in Australia and some people don't know about 800X series. We are still yet to see 800Xs here. Everybody else has them for sale but not Australia (and our friends across the ditch). Perhaps wait until the end of financial year to get better deals.
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Test Equipment / Re: Hacking the Rigol DHO800/900 Scope
« Last post by AceyTech on Today at 04:13:50 am »
Looking at the zynq 7015 pinouts along with the board layout gives some clues to the DDR SDRAM usage.

The DDR3L chip on the DHO800 is connected up to bank 13 (yellow), this will be a DDR memory controller implemented in the FPGA fabric. The gigadevice GDP2BFLM-CA is a 16-bit wide, 2133MT/s device, if clocked at it's rated frequency, that gives 34Gb/s theoretical memory bandwidth.

It looks like bank 35 (magenta) is being used for the ADC interface, 1.25Gsps @ 12-bit is 15Gb/s. Considering the memory is 16-bit wide, and there are also 16 logic analyser inputs, they could just be storing 12-bit samples as 16-bit instead of repacking, bringing the ADC sample bandwidth up to 20Gb/s.

I'm assuming that bank 34 is mostly being used for the differential LA inputs, as well as any other GPIOs/controls (based on some visible single ended signals on the top layer here too).

Bank 112 (blue) are the GTP tranceivers implementing the PCIe device on the RK3399.

The DHO800 unpopulated memory devices (orange) are specifically for the PS / ARM SoC part of the zynq chip. In most zynq applications, this memory would be the system memory for embedded linux running on the PS. In these situations, any high bandwidth data needs to pass from the FPGA fabric (PL) to the PS via some dedicated  AXI buses inside the zynq, and then handled by the PS memory controller, on a separate clock domain. While they technically have the bandwidth (4x buses of 8-16GB/s, depending on clocks), it's likely that just having a synchronous memory device directly on the FPGA fabric is much more suitable for continuously streaming data from an ADC.

It's not clear to me what the PS is being used for in this zynq. Clearly it's not running embedded linux, since the RK3399 is running the host OS, and there's no system memory on the DHO800 series. It could be running some RTOS doing measurements, stats or monitoring (with the limited 256KB of on-chip memory available to it), but I really have no idea.

Thanks for your analysis and observations.  Good to have some new eyes looking at the architecture here.

Couple things I've ascertained:  (and have data for)
  --The FPGA is hooked to the SoC(RK3399) via PCIe., and according to what I've noticed, they're only using 2 PCIe channels of the 4.  I believe all 4 lanes are routed on PCB. (1/2 & 1/2 on top & bottom)
  --There are several DDR3 parts that have been or are used on the FPGA, of varying speeds...  While the GigaDevice parts are listed at 2133, We've seen slower speed parts populated. -like 1800-1900  (makes sense that they would have a very flexible DDR controller, to accomodate a fluctuating memory market.)  I'm not 100% certain what speed they're using off the top of my head.
  -- There IS "system memory on the DHO800 series", it's 4GB of DDR4 connected to the RK3399, and is only clocked at 856Mhz

FYI: They have a console UART on PCB next to the FPGA., The logfile has FSBL and "how it's config'd" info.   You might want to poke around at the ZYNC there.

Hope this is somehow helpful. 
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