Cool, I hope it'll work with the sifive/t-head/WCH implementations. I really would not want stuff like https://discourse.llvm.org/t/rfc-prestacked-annotation-to-solve-risc-v-interrupt-stacking-mess/74120 proliferating
I don't have a problem with that proposal at all, or indeed even see the situation as a "mess".
Some people are used to hardware saved registers on other ISAs and want that feature on their RISC-V processors, and probably more manufacturers than at present will (in my opinion) waste transistors that could have been used for better things (or just use less silicon) on duplicate register sets (worse) or a FSM to stack registers.
Maybe the people who want to implement/use this will agree on a single spec for it, but as it's pretty much 100% "we think it give us a competitive advantage" thing I wouldn't hold my breath, at least in the short term.
That's pretty much inevitable with a community-owned ISA. You can see it as a disadvantage, but I see it as a strength.
And I think @jnk0le's proposal is both very easy to implement and solves the problem neatly. It makes perfect sense.