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I have some curious results using a spectrum analyzer (TinySA Ultra) to see the spectral content of the generator's signal.

The interesting part is comparing it with another generator. I have assembled a quick and dirty pulse generator, or rather a pulse shaper, made of a single 1EDN7512 high-speed MOSFET driver.
I wasn't going to use it in this role, but I noticed that it had about 300 ps rise time (at a 0..15V transition) in spice simulation without load, so I thought hmm why don't I make a pulser out of it and see what happens. I don't expect it to behave exactly the same in reality, but it must still be pretty fast: a few ns turn-on time with a 1nF load is quite something.

Its typical output resistance is specified at below 1 Ohm, so I simply placed two parallel 100 Ohm resistors in series with the output, followed by an SMA connector. All mounted tightly on a small SOT-23-5 breakout board.

Now, the spectra I see in both cases don't look quite like what the textbooks say, however, I do think that I see the "second break" point on one of them, that's the point where the frequency is supposed to be equal to 1/(pi*Tr) (assuming Tr=Tf), and it meets the expectations I think.

Here's the 1EDN7512:




A very clear roll-off after about 470 MHz (~680 ps transition time), and it's dropping down pretty much into noise* after 600 MHz.
*Not sure if it can be called noise, because the actual noise floor (when there's no input) is at or slightly below -90 dBm.

But here's what the 4 x SN74LVC1G04 pulser produces:



Barely noticeable hump at ~510 MHz (that would be ~620 ps transition time) and a gradual further decline with no obvious steps, with the power levels at those higher frequencies staying above that of the other pulser.

Both had their fundamental frequency equal and set to 1024 kHz. Output levels were also the same. There was a 20 dB attenuator between the generator and the SA input in both cases.

Not sure what to make of it other than that the second pulser apparently has more energy in higher frequencies and that the first one's transition time can very likely be derived from the spectrum.
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Test Equipment / Re: SDS800X HD Wanted Features
« Last post by KungFuJosh on Today at 08:42:43 pm »
I wonder how many use these buttons.
Any advanced user with some active Math channels.

If you find yourself with some spare time, why don't you embark on reading the second sentence of eTobey's post? I am sure you will make it through...

The particular situation shwon in eTobey's screenshot seems awkward, but is probably due to the large fonts he has enabled. The only reason for the arrows to be shown is that the arrows take up room, so the CH1 box cannot be fully shown. In this case, there should be no arrows and all four channels boxes fully visible.

With the regular, smaller fonts, omitting the arrows would not make enough room available to show an additional full info box, I believe. So in general, I am fune with keeping the arrows.

I think Rob's point was that the buttons are used, plain and simple. Different people have different workflows. Some people will hate scrolling, some people will hate the buttons.

However, I agree with you that the buttons shouldn't be there when there's only the 4 channels. The buttons should only appear when needed.
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I haven't seriously used Windows in 20 years, but I strongly suspect that any "slowness" is a matter of using right options, such as disabling "full formatting" (pointless overwriting of all space on the drive). Run it with /? first.

yes looks like it, https://learn.microsoft.com/en-us/windows-server/administration/windows-commands/format
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Thaaaat story happened in the past, it continues, and will be.

but ... damn  i missed "ULTRA HIGH PRECISION"  with isolation board .....
and ... honestly .... that board missed sticky copper foil ,  ( i assume, you know what im talking about)
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I did actually find a way to do it in the end. I meant to come back here and post an update but it slipped my mind.

The AHCI register contents memory region is actually exposed in sysfs, in
/sys/bus/pci/devices/<device id>/resource5. It is the same "Resource 5" (aka "Region 5", "BAR5") mentioned in lspci verbose output. But you can't just read that file - oh, no, that would be too easy! :P It has to be accessed using mmap IO. I found a utility on GitHub that will do so:
https://github.com/billfarrow/pcimem.

Code: [Select]
$ sudo ./pcimem /sys/bus/pci/devices/0000:01:00.0/resource5 0 w*128
/sys/bus/pci/devices/0000:01:00.0/resource5 opened.
Target offset is 0x0, page size is 16384
mmap(0, 4096, 0x3, 0x1, 3, 0x0)
PCI Memory mapped to address 0x7fffa9fbc000.
0x0000: 0xEB32FFA1
0x0004: 0x80000002
0x0008: 0x00000000
0x000C: 0x00000003
0x0010: 0x00010200
0x0014: 0x00000010
0x0018: 0x00000000
...

The arguments to the command tell it to read 128 32-bit words starting from offset zero. The AHCI register space on my particular SATA controller is 512 bytes, because it only features 2 ports. With more ports the register space will be larger.

The GHC.AE (AHCI mode enabled) register flag is bit 31 of the word at offset 0x0004. You can see here that it is set. :D
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When electrical engineers develop schizophrenia...
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Microcontrollers / Re: Divide clock by 3 on a ATF16V8B
« Last post by Benta on Today at 08:37:57 pm »
Here's a divide-by-three:

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AFAIK, 598 is just 494 with totem pole outputs -- better for gate driving.  But you might want a proper driver on it, still, anyway; it's old bipolar stuff.

Tim
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>What is the target distortion ?
I do not know yet.
It seems there is a lot you do not know. The frequency and amplitude are important info, even ballparks ?

What is the intended purpose of this signal, you must know at least that ?
eg is it to calibrate meters ?

One option is that: do not care. I can measure what the amplitude is and then do the math one way or another.

Then you need a precision rectifier. Also non trivial, but easier at low frequencies.

You can assist the LPF design, by using a shaped stepped sine generated digitally, using simple CMOS counters/gates and resistors.

Or a small MCU with a DAC, can do most of the work, at lower frequencies.  This is why the parameters matter.


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There is no need for a perfect sync betwen the CPU and PIO part. Usually this is given as the PIO clock is from a divider. Only the possible fractional divider could cause trouble.

The sync problem would appear, when the CPU runs from the PLL and than external sync FF are used to directly synchronize to an external clock. This case is triky and if possible I would avoid it because of the complications with the phase, even if the PIO clock would be the same as the PLL input clock.

The more realistic case is an external clock (e.g. 20 MHz range) to directly run the CPUs. The PIO clock could even be a bit lower to get the delays without extra code.
Chances are one can skip an external sync step, though there is possibly a tiny bit of delay modulation from the µC internal state that could lead to a little INL.
If needed / wanted an external sync with 2 flip flops (the input path is not that critical and could be direct) is not that complicated if there is no PLL involved.
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