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Repair / Re: HP 8903a "mV" problem, newbie question
« Last post by DeepLink on Today at 12:38:48 pm »
Never seen a bad relay in the units I worked on...

It is easy to check the logic circuit
The input board are controlled by the Latch board

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Test Equipment / Re: Siglent SDS800X HD Review & Demonstration Thread
« Last post by egonotto on Today at 12:36:10 pm »
Digital summation with a math function does, of course, not introduce any IMD between the two signals. You just get the sum of the two (complex) spectra, since FFT(x+y) = FFT(x) + FFT(y).

Exactly!! The separate channel digitized signals can't "see" each other, thus no IMD should be present and why we mentioned such.

Best,

Hello,

If I understand correctly, the combined signal is fed into C1 and the FFT would already show the interference of the input circuit and the ADC.

Best regards
egonotto
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Regarding the IMD tests:  I'm not sure I completely understand what is being measured / quantified about the scope here.

In my experience (and certainly in the case of spectrum analyzers and VNAs), IMD is most often measured by providing the DUT with an input signal that consists of two tones at different frequencies (F1 and F2) and then measuring the amplitudes of the close-in 3rd order products (2F1-F2 and 2F2-F1) at the DUT output relative to the amplitude of the fundamentals.  This is the used to compute the theoretical intercept of the slope of the fundamental and 3rd order products and yields the third order intercept point (IP3 or TOI).  A higher IP3 is generally desirable because it indicates greater linearity of the DUT, i.e. less IMD created by the DUT.

If I wanted to quantify the IP3 of a scope's front end, I would simply generate two tones (ideally using completely separate sources and circulators) with slightly (~1 MHz or so) different frequencies, combine them externally, and then feed that combined input signal into a single scope channel.  Then I would perform an FFT of the signal and measure the difference in amplitude between the fundamentals and above-mentioned 3rd order products and do the math (IP3 = Ptone + deltaP/2).

I can understand why we might want to quantify the linearity of a scope's front end (vertical amplifier, etc.) but I don't think I understand the methodologies / results I'm seeing here.    Sorry if I'm being dense :)
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I had a Leo Bodnar two output GPSDO for a few weeks last year for a project, it is a nice unit. Unfortunately had to return it when done.
It uses a MAX-M8Q with a SKYWORKS SI5328C jitter correction chip.
The Si5328C has loop filters from 0.05Hz to 6Hz so it can clean up the UBLOX output.
I have been experimenting with the SI5328C to see if I can get similar results. but not quite there yet.
Ed, I have the dual BNC Leo Bodnar unit. The level of frequency jitter I measured is around +/- 4 parts in 10^10, which doesn't sound much, but is around ten times worse than my home made Lars Walenius unit. Both measured at 10 MHz. I tried powering the LB from both a wall wart phone charger (USB) and from a linear power supply to the DC input socket, both produced the same level of jitter.

When you run out of things to test with the PFA, you can have endless fun measuring inductors, capacitors and filters with it configured as a VNA  :-DD

SJ
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Beginners / Re: identifying Ferrite bead value?
« Last post by samholloway on Today at 12:30:57 pm »
The bead issue is a symptom and not the cause of your issues.

check for short circuit or voerloand on DC power.

Can you please add photos of the bead and blown via.






Jon
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Repair / Re: HP 8903a "mV" problem, newbie question
« Last post by Agosto on Today at 12:30:36 pm »
Thank you! Great info! I was going through the service manual and BD2 and also thought that the issue must be in the input section. Never worked on an HP so this is new to me. I will do as suggested and use special function to trigger the suitable input. So you think the issue is on the input board but not related to the "logic control"?
I did see some Reed-Relais on the board. Mostly for attenuation, though. I am thinking I should look at the gain section.
Do you know a source for these relays? I googled them to no avail...

Thanks again for your input. Seems that I am on the right track. I will only be able to work on this unit after my return from a trip in two weeks. I might need your help again...!
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Microcontrollers / Re: SD Card reliability in SPI mode
« Last post by faststoff on Today at 12:30:15 pm »
I may be missing something simple, but surely talking to an SD card via the serial interface is no different to using say FatFS and talking to an SPI flash memory chip.

You will be limited by the flash endurance; typically 100k writes to the same block, plus other limitations like adjacent line interference which needs blocks to be periodically refreshed.

If you want a FAT file system (and you do if you also want it to look like a removable drive to windoze, via USB MSC device profile) then auto wear levelling in the flash media is the only way.

The situations you describe are vastly different!

The key concept is who is responsible for implementing the flash transition layer - FTL.
Wear leveling is only one part of a range of things the FTL is responsible for (ECC, bad-block management, buffering of blocks for writes due to the nature of NAND chips...). See here for a more complete description or search for FTL (https://msreekan.com/2014/01/15/sdcard/).

Going with a bare NAND (ie. not NOR) memory chip makes you responsible for dealing with all this hand-holding. Speaking from experience, this is also why file systems targeting bare NAND memories requires vastly more RAM than FAT32-only systems, as they will need big buffers to hold flash content in RAM during e.g. an update to a block.
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My suggestion would be a (linear) Siglent SPD3303X for a new supply - I have a couple and am very pleased with their performance.  Although if you don't mind analog meters a vintage HP, Kikusui or such are very, very good performers and are pretty much bulletproof.

Hal
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Environmental factors such as temperature can also influence the performance of electronic components, so try to maintain a stable testing environment.
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