if(fpgasettings.fw_FPGA > 1)
{
//Write the command to set the pretrigger_samples to the FPGA
fpga_write_cmd(0x0B);
fpga_write_short(fpgasettings.settriggerpoint/2);
//Write the command to set the total_samples to the FPGA
fpga_write_cmd(0x0C);
fpga_write_short(fpgasettings.totalsamples/2);
//set time to automode
fpga_set_time_base(scopesettings.timeperdiv);
}
//short time base
void fpga_set_time_base(uint32 timebase) //len pre rezim auto, urcuje max cas po ktory sa odoberaju vzorky
{
//Make sure setting is in range
if(timebase < (sizeof(timebase_settings) / sizeof(uint32)))
{
//Write the command to set the short time base data to the FPGA
fpga_write_cmd(0x0E);
//Table settings ranges from setting 0 (200mS/div) to 23 (5nS/div)
if(fpgasettings.fw_FPGA == 1)
{
fpga_write_int(timebase_settings[timebase]);
}
else fpga_write_int(scopesettings.samplecount);//3000-6000-9000-15000
}
}
uint16 fpga_get_version(void)
{
uint16 fw_version;
fpgasettings.fw_FPGA = 0;
fpga_write_cmd(0x06);
fw_version = fpga_read_short();
if(fw_version == 0x1432) fpgasettings.fw_FPGA = 1; //fnirsi fw in FPGA
if(fw_version == 0x1532) fpgasettings.fw_FPGA = 2; //PECO fw in FPGA AL3
if(fw_version == 0x1632) fpgasettings.fw_FPGA = 3; //PECO fw in FPGA EF2
return(fw_version);
}
const uint32 timebase_settings[35] =
{//long time base
1800, //50s/div
1800, //20s/div
1800, //10s/div
1800, //5s/div
1800, //2s/div
1800, //1s/div
1800, //500ms/div
1800, //200ms/div
1800, //100ms/div 9
1800, //50ms/div //not used
1800, //20ms/div //not used
//sort time base ONLY mode AUTO trigger, set sample time
5000, //200ms/div 500Sa/s 12
5000, //100ms/div 1KSa
5000, // 50ms/div 2KSa
5000, // 20ms/div 5KSa (Was 800, but that does not yield enough samples)
5000, // 10ms/div 10KSa
5000, // 5ms/div 20KSa
5000, // 2ms/div 50KSa
5000, // 1ms/div 100KSa
5000, //500us/div 200KSa
5000, //200us/div 500KSa
8192, //100us/div 1MSa//5596
5596, // 50us/div 2MSa
9692, // 20us/div 5MSa
21980, // 10us/div 10MSa
21980, // 5us/div 20MSa
83420, // 2us/div 50MSa
206300, // 1us/div 100MSa
411100, //500ns/div 200MSa
411100, //200ns/div
411100, //100ns/div
411100, // 50ns/div
411100, // 20ns/div
411100, // 10ns/div
411100 // 5ns/div 35
}; Table for fnirsi FW fpga,
Table for fnirsi FW fpga, I could create a similar one for FPGA firmware
Home
Help
Search
Login
Register
