FNIRSI-1013D "100MHz" tablet oscilloscope

[ObsoleteDIY]

varies depending on the setting 3000-6000-9000-12000-15000

try this

Hi Atlan

new FW DSO 1.00o6 works better  but there is still some problem. Please watch the video. Thanks

1. Set Memory 3000 + Triger position 50%(fpgasettings.settriggerpoint/2 = 750?) result = Auto trigger works

2. Set Memory 12000 + and dont change Triger position(fpgasettings.settriggerpoint/2=750?) = result Auto trigger works

3. Set Memory 12000 + and set Triger position 50% (fpgasettings.settriggerpoint/2=3000?) = Auto trigger does not work

Can you confirm that Auto trigger works properly only with setting fpgasettings.settriggerpoint/2 = 750? Should I make some change in FW FPGA?

https://drive.google.com/file/d/1EphN3WHYtWCDBnCc-WKJbu9wlWzeA8AZ/view?usp=sharing

[Atlan]

sorry, been absent for a while - what is the latest firmware (without FPGA) - is it "fnirsi_1013d.bin v0.26v9.txt.bin"?

Do I need any extra hardware for the "FNIRSI1013D-APP-beta10\FNIRSI 1013D-APP-beta10.html" ?
How do I setup ?

greetings

It will work, but only as a demonstration, only with the firmware that is in the video. Since the firmware was written by a Chinese, the implementation looks like this anyway. A million bytes of data are transferred unnecessarily. The PC program would have to be modified to fully support the 1013D hardware, and it would also be appropriate to cancel the sending of large amounts of data.

[doublerock385]

Attached is a capture of an SPI transaction between a CH341A and a W25Q128JV flash chip. Channel 1 is the CS (chip select) line and channel 2 is the SCLK (clock). I'm wondering why the clock signal looks quite irregular? I think it should be a 50% duty cycle. Everything works between the programmer and the chip. This was with the stock firmware. The custom firmware was not working for this one.

[Atlan]

This was with the stock firmware. The custom firmware was not working for this one.

I don't know what didn't work with what, or what you did. Too little information about 1013D and your work.
Uploading the contents of the FPGA EF2 (fpga.bin) to the flash memory for the uP or the flash memory for the FPGA AL3 will not work.

The CH341 works as programmed by the PC software programmer.

[ObsoleteDIY]

varies depending on the setting 3000-6000-9000-12000-15000

try this

Hi Atlan,

I’m testing FW DSO1.00o6 + new FPGA FW EF2L 0x1632 and found some problems. The issues occur when Memory is set to 12000 in the menu:

Basic calibration takes very long — over a minute.
If no probes are connected and I use Auto Set, it works only once. If I use Auto Set several times, the device freezes.

These problems do not occur with FW DSO1.00o5. Could you please check if the same problems occur on your device?

1.What values ​​does FW DSO 1.00o6 send to the FPGA register time_base_cnt?
2.Can you please tell me from what read address does FW DSO 1.00o6 start reading the sample memory when  register *trigger_address = 300* was set in the FW FPGA. (Menu options Memory 12000, Triger position 25%)           

[ObsoleteDIY]

So try to calculate it. 10Msa,50us/div. Signal 1kHz. Number of samples 3000. Sampling starts at a random time and only 3000 samples are taken, do you think that one whole period of the signal will appear in those 3000 samples? Also calculate that if the trigger is at 50% memory, you need the Trigger value and edge type settings to be in the last 1500 samples.

Hi,

I analyzed the EF2L45 FPGA firmware to understand how AUTO TRIGGER works. I don’t see the FPGA measuring the signal period — it only detects the edge.

After reset, the FPGA starts writing to memory from address 0. When the number of stored samples is greater than *pretrigger_samples*, the trigger on the selected rising/falling edge is enabled.

The FPGA writes to memory in a circular way until it detects the edge or until register *time_base_cnt* expires.

If the edge is detected, it saves the current memory address into the*trigger_address* register and continues writing until *posttrigger_samples* are stored.

The DSO firmware should read memory
from
*trigger_address - pretrigger_samples*
to
*trigger_address + posttrigger_samples*.

The MEMORY setting (3000–12000) and Trigger position (25–75%) only change the number of samples before and after the trigger.I don’t understand why setting Memory to 12,000 and Trigger position to 25% causes AUTO TRIGGER not to work correctly.

The issue is likely in how the DSO firmware reads or processes the memory. I tried making various modifications to the EF2L45 FPGA firmware, but the result is always the same — AUTO TRIGGER still does not work correctly.

If necessary, I can modify the EF2L45 FPGA firmware to make it better work. Could you please check how AUTO TRIGGER works in the FW DSO and send me a description of how AUTO TRIGGER works in the DSO firmware? Thank you.

[Atlan]

If I have time, I'll write to you tonight.

[Etrius]

Hello everyone. Thanks to the contributions of the developers on this forum, I decided to use their work to give new life to my 1013d. After testing and being thrilled with all the improvements implemented in the version available on GitHub, I'd also like to try the new version (1.00).
However, I need to understand the hardware modifications required to program the FPGA. I've looked at the various posts but haven't really figured out what to do. I've seen images of hardware modifications, unsoldering flash, and using the bluepill (STM32F103C8), but I'm just confused. Could someone please explain what I need to do?
I also noticed that the FPGA model in my device has been erased and replaced with the code 017325203512. Is it important to know the real model of my FPGA?
Thank you for your attention.

[ObsoleteDIY]

Hello everyone. Thanks to the contributions of the developers on this forum, I decided to use their work to give new life to my 1013d. After testing and being thrilled with all the improvements implemented in the version available on GitHub, I'd also like to try the new version (1.00).
However, I need to understand the hardware modifications required to program the FPGA. I've looked at the various posts but haven't really figured out what to do. I've seen images of hardware modifications, unsoldering flash, and using the bluepill (STM32F103C8), but I'm just confused. Could someone please explain what I need to do?
I also noticed that the FPGA model in my device has been erased and replaced with the code 017325203512. Is it important to know the real model of my FPGA?
Thank you for your attention.

If you want to install alternative content into an FPGA you need to identify what type of FPGA you have in your device. See page 140-142 in this thread, you will find some photos there. Without a photo of your PCB it is difficult to advise.

[Etrius]

Thanks for the reply. I looked more carefully at the posts you recommended, but I still don't understand much. Probably because I have very little knowledge of FPGAs and how to program them. This is a picture of my device but the logo is erased. I have no idea how to find the model number.

[ObsoleteDIY]

Your FPGA is probably AL3. Your PCB looks similar to PCBs that have AL3+SPI FLASH. Read Atlan's posts in this thread(page 140-142) and read the *Guide to firmware* on GIThub. https://github.com/Atlan4/Fnirsi1013D/tree/main/Guide%20to%20firmware

[Etrius]

Thanks for your time.
However, I need to understand whether modifying the FPGA requires hardware modifications or whether it's just a software process using the V0.8 bootloader (already installed). Reading the various posts has left me very confused.

[pcprogrammer]

Thanks for your time.
However, I need to understand whether modifying the FPGA requires hardware modifications or whether it's just a software process using the V0.8 bootloader (already installed). Reading the various posts has left me very confused.

It needs hardware modification. The system as is has a separate FLASH for the FPGA that can't be written from the firmware. By removing the MCU FLASH and soldering the signals from the FPGA FLASH to the signals of the MCU FLASH, the firmware can then update the FPGA FLASH. This does mean that the old firmware is not available anymore.

And yes your FPGA will most likely be the AL3-10. Your board looks just like mine. Only the (serial) number on the FPGA is different.

[Etrius]

Thanks for your help. Can you tell me if I've identified the various components correctly?

[Etrius]

After doing some research online, I think I've correctly identified the two flash memories. What I marked as the JTAG connector is incorrect, but it shouldn't be needed. Now I need confirmation on the steps I need to follow:
1) Unsolder the flash MCU (25Q16)
2) Unsolder the flash FPGA (25Q80)
3) Solder the flash FPGA (25Q80) in place of the flash MCU
4) Turn on the oscilloscope
5) Write the flash FPGA (25Q80) using the V0.8 bootloader
6) Turn off the oscilloscope
7) Unsolder the flash FPGA (25Q80)
8 ) Solder the flash FPGA (25Q80) in its original position
9) Solder the flash MCU (25Q16) in its original position
Is this a possible correct procedure?

[pcprogrammer]

After doing some research online, I think I've correctly identified the two flash memories. What I marked as the JTAG connector is incorrect, but it shouldn't be needed. Now I need confirmation on the steps I need to follow:
1) Unsolder the flash MCU (25Q16)
2) Unsolder the flash FPGA (25Q80)
3) Solder the flash FPGA (25Q80) in place of the flash MCU
4) Turn on the oscilloscope
5) Write the flash FPGA (25Q80) using the V0.8 bootloader
6) Turn off the oscilloscope
7) Unsolder the flash FPGA (25Q80)
8 ) Solder the flash FPGA (25Q80) in its original position
9) Solder the flash MCU (25Q16) in its original position
Is this a possible correct procedure?

This is an option, but not the proper one. Instead of desoldering the FPGA FLASH, run some wires from it to the MCU FLASH. For this the two empty header footprints can be used. Do desolder the MCU FLASH. Atlan wrote about this somewhere in this thread.

They are located near both FLASH chips and make things easier. The identification of both chips on your board is correct, but the FPGA JTAG marking is indeed wrong. This is the "I2C" header for the special IC that FNIRSI uses for making cloning the scope harder.

Once the new FPGA configuration is in place, for as far as I understood, the original firmware won't work properly any more, so no need to resolder the FLASH MCU.

[Etrius]

Thanks for your time. I've been revisiting the various posts, and now they're finally clear to me. Initially, I didn't understand the context, and they were just confusing. You gave me the right input.
As a precaution, I won't use the original FPGA flash, but another 25Q80 that I'll clone before soldering it (that might be helpful).
After the FPGA upgrade, is the version I should be displaying 1532 (my FPGA is an AL3-10)?

[Atlan]

varies depending on the setting 3000-6000-9000-12000-15000

try this

Hi Atlan

new FW DSO 1.00o6 works better  but there is still some problem. Please watch the video. Thanks

1. Set Memory 3000 + Triger position 50%(fpgasettings.settriggerpoint/2 = 750?) result = Auto trigger works

2. Set Memory 12000 + and dont change Triger position(fpgasettings.settriggerpoint/2=750?) = result Auto trigger works

3. Set Memory 12000 + and set Triger position 50% (fpgasettings.settriggerpoint/2=3000?) = Auto trigger does not work

Can you confirm that Auto trigger works properly only with setting fpgasettings.settriggerpoint/2 = 750? Should I make some change in FW FPGA?

https://drive.google.com/file/d/1EphN3WHYtWCDBnCc-WKJbu9wlWzeA8AZ/view?usp=sharing

start

Code: [Select]

void fpga_do_conversion(void)
{
  scopesettings.conversion_done = 0;    //flag for conversion, 0-start
 
  //Check if sampling with trigger system enabled
  if(scopesettings.samplemode == 1)
  {
    //Enable trigger system???
    fpga_write_cmd(0x0F);
    fpga_write_byte(0x00);
  }
  else
  {
    //Disable the trigger circuit??
    fpga_write_cmd(0x0F);
    fpga_write_byte(0x01);
  }
 
  //Reset the sample system
  fpga_write_cmd(0x01);
  fpga_write_byte(0x01);
 
  //Send check on ready command
  fpga_write_cmd(0x05);
 
  //Wait for the flag to become 1
  while((fpga_read_byte() & 1) == 0);
 
  //Test again to make sure it was no glitch?????
  //while((fpga_read_byte() & 1) == 0);
 
  //posielat ked je sytem v resete, aby neprepisal udaje zachodu
 
  if(fpgasettings.fw_FPGA > 1)
  {
    //Write the command to set the pretrigger_samples to the FPGA
    fpga_write_cmd(0x0B);
    fpga_write_short(fpgasettings.settriggerpoint/2);

    //Write the command to set the total_samples to the FPGA
    fpga_write_cmd(0x0C);
    fpga_write_short(fpgasettings.totalsamples/2);

    //set time to automode
    fpga_set_time_base(scopesettings.timeperdiv);
  }
 
  //Done with reset
  fpga_write_cmd(0x01);
  fpga_write_byte(0x00);
}


Code: [Select]

void fpga_set_time_base(uint32 timebase) //len pre rezim auto, urcuje max cas po ktory sa odoberaju vzorky
{
  uint32 set_time_automode = 0;
   
  //Make sure setting is in range
  if(timebase < (sizeof(timebase_settings) / sizeof(uint32)))
  {
    //Write the command to set the short time base data to the FPGA
    fpga_write_cmd(0x0E);
   
    //Table settings ranges from setting 0 (200mS/div) to 23 (5nS/div)
    if(fpgasettings.fw_FPGA == 1)
    {
    fpga_write_int(timebase_settings[timebase]);
    }
    else
    {
      if(timebase < 21)  set_time_automode = scopesettings.samplecount;
      if(timebase < 24)  set_time_automode = scopesettings.samplecount * 2;
      if(timebase == 24) set_time_automode = scopesettings.samplecount * 4;
      if(timebase == 25) set_time_automode = scopesettings.samplecount * 6;
      if(timebase == 26) set_time_automode = scopesettings.samplecount * 10;
      if(timebase == 27) set_time_automode = scopesettings.samplecount * 20;
      if(timebase == 28) set_time_automode = scopesettings.samplecount * 40;
      if(timebase == 29) set_time_automode = scopesettings.samplecount * 80;
      if(timebase > 29)  set_time_automode = scopesettings.samplecount * 160;
         
      fpga_write_int(set_time_automode);
    }
  }
}
REad data

Code: [Select]

    //Get trigger point information
    //Later on used to send to the FPGA with command 0x1F
    data = fpga_prepare_for_transfer();


Code: [Select]

if(fpgasettings.fw_FPGA == 1)
    {
      if(data < 750)
      {
        //Less then 750 make it bigger
        data = data + 3345;
      }
      else
      {
        //More then 750 make it smaller
        data = data - 750;
      }
    }
   
    if(fpgasettings.fw_FPGA == 2) //fpga AL3 or EP4
    {
       if(data < (fpgasettings.settriggerpoint/2))
       {
         //Less then 750 make it bigger
         data = data + 7441;
       }
       else
       {
         //More then 750 make it smaller
         data = data - (fpgasettings.settriggerpoint/2);
       }   
    }
   
    if(fpgasettings.fw_FPGA == 3) //fpga EF2
    {   
      if(data < (fpgasettings.settriggerpoint/2))
      {
          data = data + 5393;
      }
      else
      {
          data = data - (fpgasettings.settriggerpoint/2);
      }
    }

    //Only need a single count variable for both channels, since they run on the same sample rate
    //This can be changed to a global define
    scopesettings.nofsamples  = fpgasettings.totalsamples/2;//SAMPLES_PER_ADC;//5000
    scopesettings.samplecount = fpgasettings.totalsamples;//SAMPLE_COUNT;//10000

      //Get the samples for channel 1
      fpga_read_sample_data(&scopesettings.channel1, data);


Code: [Select]

uint16 fpga_prepare_for_transfer(void)
{
  uint32 data;
 
  //Send the command for getting some data (trigger address) from the FPGA
  fpga_write_cmd(0x14);
 
  //Just read a short, and with 0x0FFF and add 2
  //Have to see if the add 2 is needed
  //data = (fpga_read_short() & 0x0FFF) + 2;   
  data = (fpga_read_short() & 0x1FFF);  //change 11.12.2025
 
  return(data & 0x1FFF);
}


Code: [Select]

void fpga_read_sample_data(PCHANNELSETTINGS settings, uint32 triggerpoint)
{
   //Send command 0x1F to the FPGA followed by the translated data returned from command 0x14
  fpga_write_cmd(0x1F);
  fpga_write_short(triggerpoint);
 
  //Read the data for the first ADC. Samples start on the second location, skipping every other sample
  fpga_read_adc_data(settings);


Code: [Select]

void fpga_read_adc_data(PCHANNELSETTINGS settings)
{
  //Set the bus for reading
  FPGA_BUS_DIR_IN();
 
  //Set the control lines for reading a command
  FPGA_DATA_READ();
 
  //Set the number of samples to read
  count = scopesettings.nofsamples;
  //count = fpgasettings.totalsamples/2;
 
  //Read the data as long as there is count
  while(count)
  {
    //Clock the data to the output of the FPGA
    FPGA_PULSE_CLK();

    //Read the data
    sample = FPGA_GET_DATA();
   


[pcprogrammer]

Thanks for your time. I've been revisiting the various posts, and now they're finally clear to me. Initially, I didn't understand the context, and they were just confusing. You gave me the right input.
As a precaution, I won't use the original FPGA flash, but another 25Q80 that I'll clone before soldering it (that might be helpful).
After the FPGA upgrade, is the version I should be displaying 1532 (my FPGA is an AL3-10)?

On that I have no idea. I don't follow Atlan's work that closely, so more a question for him to answer.

[ObsoleteDIY]

Hi,

is the value *data* the starting address for reading from FPGA memory? If so please check this calculation.

    if(fpgasettings.fw_FPGA == 3) //fpga EF2
    {   
      if(data < (fpgasettings.settriggerpoint/2))
      {
          data = data + 5393;
      }
      else
      {
          data = data - (fpgasettings.settriggerpoint/2);
      }
    }

should the calculation for a circular buffer look like this?

    if(fpgasettings.fw_FPGA == 3) //fpga EF2
    {   
      if(data < (fpgasettings.settriggerpoint/2))
      {
          data = 6144 - ((fpgasettings.settriggerpoint/2)- data);
      }
      else
      {
          data = data - (fpgasettings.settriggerpoint/2);
      }
    }

I apologize if I didn't understand the code correctly. Thanks

[Atlan]

Data is the address where the trigger is found. If the trigger is 50% and the number of samples is 3000, the address where the trigger is located is taken and 1500 is subtracted, the given address is sent to the fpga. . And when data is read from the fpga after 1500 samples, the trigger will be located in the middle of the samples (3000) the joke is that one address corresponds to 16bit TJ channel A and B of the adc converter. So the address is divided by two.

[ObsoleteDIY]

Sorry, I don't understand why the calculation uses the constant 5393 when the value (fpgasettings.settriggerpoint/2) can range from 750 to 1500. Please give an example of what is calculated if it is set in the DSO menu - Memory 12000, Trigger position 25% and readed Triger address(data) =1000

[Atlan]

Code: [Select]

if(fpgasettings.fw_FPGA == 3) //fpga EF2
    {   
      if(data < (fpgasettings.settriggerpoint/2))
      {
          data = 6143 - (fpgasettings.settriggerpoint/2) + data;
      }
      else
      {
          data = data - (fpgasettings.settriggerpoint/2);
      }
    }
This is how it should be right. I'm not sure if it's 6143 or 6144. But when I played with it before, the correct value was - 1, The number of samples doesn't matter. We are actually looking for a trigger in the circular memory. Of course, we also need to display the samples before the trigger 25 50 75%, so the given number is subtracted from the place where the trigger is in the circular memory. The obtained number is used as the start from which the samples are read into the uP memory. If we have samples in the uP memory, a check is also performed to fine-tune the trigger location for its placement in the center of the horizontal cursor. (I have to check there if there is no error too)

In the basic and automode calibration modes, the Trigger is not used and the number of samples is 1000. Due to the increase in speed, it is possible that the given setting is overwritten, see the code for auto Trigger mode, the Sampling duration is extended there. I will upload a modified version of the DSO firmware here. So try to see if the conversion will be ok.

[Atlan]

Try.

O7 trigger calculation fix.
O8 removed longer sample reading in auto trigger mode.

[ObsoleteDIY]

Hi,

Thank you.I will test

I have prepared new firmware for EF2L FPGA. I have changed and tested the content many times, please see my changes. The file *zaklad.v* is attached.
1. I added calculation of *trigger address* when a time_base_out occurred (previously the trigger address was set to a fixed value)
2. I added blocking of *time_base_out* if a trigger was found (previously the trigger address could be overwritten)