FNIRSI-1013D "100MHz" tablet oscilloscope

[ObsoleteDIY]

Hi,

I am working the new FW 1601 for the FPGA EF2L45. I changed the trigger from single channel A to dual channel A+B. I also added trigger arming so the trigger does not start if the signal is not at the correct level.

The trigger should be more stable and accurate, but I do not see much difference. I see a stable signal but the frequency xxx is displayed.

Atlan, do we need to make any changes in the DSO firmware for the dual-channel trigger to work ? Thanks

[ObsoleteDIY]

Hi,

I am attaching a comparison video of EF2L FW 0x1600 and FW 0x1601. It's a small difference, but maybe less hopping at 100kHz / 400ns pulse?

https://drive.google.com/file/d/1txvy-bqILvfMLbsdvJpm9_CGVEK_nUjp/view?usp=sharing

[Atlan]

Code: [Select]

uint16 fpga_get_version(void)
{
  uint16  fw_version;
  fpgasettings.fw_FPGA = 0;
 
  fpga_write_cmd(0x06);
  fw_version = fpga_read_short();
 
  uint8 family = (fw_version >> 12);  // upper byte = family FPGA
 
  if(family == 0x1)      fpgasettings.fw_FPGA = 1;  //fnirsi fw in FPGA
  else if(family == 0x2) fpgasettings.fw_FPGA = 2;  //PECO fw in FPGA EF2
  else if(family == 0x3) fpgasettings.fw_FPGA = 3;  //PECO fw in FPGA AL3
  else if(family == 0x4) fpgasettings.fw_FPGA = 4;  //PECO fw in FPGA EP4

  return(fw_version);
}0xZYYY z is family YYY firmware version -001 to 999 only digit

trigger MIN is 500 in memory, MAX is setsamples-500

[Atlan]

Hi,

I am attaching a comparison video of EF2L FW 0x1600 and FW 0x1601. It's a small difference, but maybe less hopping at 100kHz / 400ns pulse?

https://drive.google.com/file/d/1txvy-bqILvfMLbsdvJpm9_CGVEK_nUjp/view?usp=sharing

use FW1.00p1 and dots mode for ch1, linear skipping samples!

Give me the modified code so I can see it on the pages right away and not have to download and open the file. Just make the changes related to what you mean by channel A+B

Basically, it was done so that the trigger level was compared only on channel A (which is inconvenient because there is a lower probability of capturing the trigger - i.e. more samples must be taken to hit the trigger)

The FPGA handles all of this. The DSO firmware doesn't handle this - it just sends the trigger value at which it wants the capture to occur.

[ObsoleteDIY]

Hi,

I tested FW1.00p1 in DOT mode and the displayed waveform is more stable. Settings *trigger MIN is 500 in memory, MAX is setsamples-500* maybe it would look better if the trigger position remained in the center of the screen = *trigger MIN is 750 in memory, MAX is setsamples-750*?
Sorry, my zaklad.v file contains a lot of debugging changes. I am sending all the changes, please check them and choose which ones to use.( or use all changes #NEW 0x2001)

Code: [Select]

//  wire trigger_rise_enable;
//  wire trigger_fall_enable;

// wire cur_greater_equal_lev;      //Signal active when the current sample is less then or equal to the set trigger level
// wire prev_less_equal_lev;        //Signal active when the previous sample is less then or equal to the set trigger level 
//#NEW 0x2001 
  wire rise_edgeA;                   //Signal active when rise edge detect from adcA
  wire rise_edgeB;                   //Signal active when rise edge detect from adcB
  wire fall_edgeA;                   //Signal active when fall edge detect from adcA
  wire fall_edgeB;                   //Signal active when fall edge detect from adcB
  wire armi_riseA;                   //Arming Triger - Signal active when current sample adcA is greater to the set trigger level
  wire armi_riseB;                   //Arming Triger - Signal active when current sample adcB is greater to the set trigger level
  wire armi_fallA;                   //Arming Triger - Signal active when current sample adcA is less to the set trigger level
  wire armi_fallB;                   //Arming Triger - Signal active when current sample adcB is less to the set trigger level 
  wire trigger_detect;               //Signal active when adcA or AadcB triger detect
  wire trigger_enable;               //Signal active when signal level ready
  wire [12:0] postrigger_samples;   

//  reg [7:0] trigger_data;
 
//  reg [7:0] trigger_previous = 0;          //On reset set to the inverted trigger edge for detecting the trigger
//#NEW 0x2001   
  reg [7:0] trigger_dataA;   
  reg [7:0] trigger_dataB; 
  reg [7:0] trigger_previousA = 0;           
  reg [7:0] trigger_previousB = 0;     



Code: [Select]

//   assign time_base_timeout = (time_base_cnt > time_base_set);   
//#NEW 0x2001 disable timeout when sampling_triggered for complete sampling posttriger?
   assign time_base_timeout = (time_base_cnt > time_base_set) & (~sampling_triggered);

//  assign sampling_enable = ~(
//    (sampling_triggered && (addr_delta >= total_samples - pretrigger_samples))//);  // post-trigger complete
//         || (~trigger_mode && time_base_timeout)                                    // auto mode timeout
//#NEW 0x2001 
  assign postrigger_samples = (total_samples - pretrigger_samples);         
  assign sampling_enable = ~(
            (sampling_triggered & (addr_delta >= postrigger_samples))//);  // post-trigger complete
         | (~trigger_mode & time_base_timeout)  // auto mode timeout                                     
                  );     

// assign trigger_check_enable = ((~sampling_triggered & sampling_half_way));
//#NEW 0x2001 
  assign trigger_check_enable = (sampling_half_way);



Code: [Select]

//Sampling triggered detect

// Previous states
//  assign prev_less_equal_lev = trigger_previous < trigger_level;
//  assign cur_greater_equal_lev = trigger_data >= trigger_level;
//  assign cur_less_equal_lev = trigger_data < trigger_level;

// Enable signals
//  assign trigger_rise_enable = (~trigger_edge & prev_less_equal_lev) | trigger_detect_enable;
//  assign trigger_fall_enable =  (trigger_edge & ~prev_less_equal_lev) | trigger_detect_enable;

// Rising edge: previous ≤ level, current ≥ level
//  assign trigger_rise_detect = (~trigger_edge & prev_less_equal_lev & cur_greater_equal_lev);
// Falling edge: previous ≥ level, current ≤ level
//  assign trigger_fall_detect = (trigger_edge & ~prev_less_equal_lev & cur_less_equal_lev);


//  always @(posedge clk_200MHz) begin //clk_RAM  sample_write_clock
//    if(sample_system_reset == 1) begin
//        sampling_triggered <= 0;
//        trigger_detect_enable <= 0;
//    end else if(trigger_check_enable == 1) begin
//        sampling_triggered <= sampling_triggered | trigger_rise_detect | trigger_fall_detect;
//        trigger_detect_enable <= trigger_rise_detect | trigger_fall_detect;
//    end
//  end

//------------------------------------------------

//#NEW 0x2001 
  assign rise_edgeA = (trigger_previousA < trigger_level) & (trigger_dataA >= trigger_level);
  assign rise_edgeB = (trigger_previousB < trigger_level) & (trigger_dataB >= trigger_level);   
  assign armi_riseA = (trigger_dataA < trigger_level) & (trigger_previousA < trigger_level);     
  assign armi_riseB = (trigger_dataB < trigger_level) & (trigger_previousB < trigger_level);           
  assign fall_edgeA = (trigger_previousA > trigger_level) & (trigger_dataA <= trigger_level);
  assign fall_edgeB = (trigger_previousB > trigger_level) & (trigger_dataB <= trigger_level); 
  assign armi_fallA = (trigger_dataA > trigger_level) & (trigger_previousA > trigger_level);   
  assign armi_fallB = (trigger_dataB > trigger_level) & (trigger_previousB > trigger_level);   

  assign trigger_enable = trigger_edge ? (armi_fallA & armi_fallB) : (armi_riseA & armi_riseB);   
  assign trigger_detect = trigger_edge ? (fall_edgeA | fall_edgeB ) : (rise_edgeA | rise_edgeB );
 
  always @(posedge clk_200MHz) begin //clk_RAM  sample_write_clock
    if(sample_system_reset == 1) begin
        sampling_triggered <= 0;
        trigger_detect_enable <= 0;
    end else begin
        trigger_detect_enable <= (trigger_detect_enable | trigger_enable) & (trigger_check_enable == 1);       
        sampling_triggered <= (sampling_triggered | trigger_detect) & trigger_detect_enable;
    end       
  end


Code: [Select]

//------------------------------------------------
//  always @(posedge sample_write_clock) begin //clk_200MHz clk_RAM  sample_write_clock clk_ADC90 clk_ADC
//    if (sample_system_reset)
//       begin
//         trigger_previous <= 0;
//         trigger_data     <= 0;
//       end
//    else
//       begin
//         //sample from the previous cycle
//         trigger_previous <= trigger_data;
//         //current sample
// trigger_data <= trigger_channel ? i_adc2A_d : i_adc1A_d;
//       end
//  end
//#NEW 0x2001
  always @(posedge sample_write_clock) begin //clk_200MHz clk_RAM  sample_write_clock clk_ADC90 clk_ADC
    if (sample_system_reset)
       begin   
         trigger_previousA <= trigger_level;
         trigger_dataA     <= trigger_level;       
         trigger_previousB <= trigger_level;
         trigger_dataB     <= trigger_level;   
       end
    else
       begin
         //sample from the previous cycle
         trigger_previousA <= trigger_dataA;       
         trigger_previousB <= trigger_dataB;       
         //current sample     
         trigger_dataA <= trigger_channel ? i_adc2A_d : i_adc1A_d;                   
         trigger_dataB <= trigger_channel ? i_adc2B_d : i_adc1B_d;
       end
  end


Code: [Select]

//Sampling half way detect

  always @(posedge sample_write_clock)
    begin
      if(sample_system_reset == 1)
        sampling_half_way <= 0;
      else         
//       sampling_half_way <= (sample_write_address >= pretrigger_samples) || sampling_half_way;         
//#NEW 0x2001 (pretrigger_samples-1) triger arming and (pretrigger_samples) triger ready
       sampling_half_way <= (sample_write_address >= pretrigger_samples-1) || sampling_half_way;   
     
    end


Code: [Select]

//Capture of the trigger address

  always @(posedge sample_write_clock)
    begin
      if(sample_system_reset == 1)
        trigger_address <= 0;         
   
      else if(sampling_triggered == 0)
        begin     
          if (~trigger_mode && time_base_timeout)
//            trigger_address <= pretrigger_samples;                 
//#NEW 0x2001   
           begin         
             if (trigger_read_address >= postrigger_samples) trigger_address <= (trigger_read_address-postrigger_samples);           
             else trigger_address <=  (MEM_SIZE - (postrigger_samples-trigger_read_address));               
           end
           else
             trigger_address <= trigger_read_address;
        end
    end


[dougduck]

use FW1.00p1 and dots mode for ch1, linear skipping samples!

Is this version only for EF2? I tried it with AL3 and it didn’t work.
Is it possible to downgrade using the Updater?

[ObsoleteDIY]

If you want to use DSO version 1.00p0 or DSO 1.00p1 you must have a new FW version in the FPGA. If you have not updated the FPGA FW you must use DSO1.00o

[dougduck]

If you want to use DSO version 1.00p0 or DSO 1.00p1 you must have a new FW version in the FPGA. If you have not updated the FPGA FW you must use DSO1.00o

What FPGA version is used for AL3? Is it the same as for EF2?

[ObsoleteDIY]

Hi,

FW for FPGA AL3,EF2L and EP4 are not the same.

The latest released FW for FPGA AL3 is version 0x1532 and works only up to FW DSO 1.00o8.

For FW DSO 1.00p0 or FW DSO 1.00p1 you need FW FPGA EF2L 0x2000 or FW FPGA AL3 0x3000 or FW FPGA EP4 0x4000. Version 0x1yyy means OEM FNIRSI.

Atlan only posted FW FPGA EF2L 0x2000 to the forum for testing. (Atlan generated FW DSO 1.00p0-1 so that I could test the new FW FPGA EF2L 0x2001).

If you install FW DSO 1.00p0 or FW DSO 1.00p1 and leave the old FW FPGA AL3 0x1532 or the old FW FPGA EF2L 0x1632, your oscilloscope will not work.

I understand that changing the FW FPGA numbering causes problems/misunderstandings for users. Sorry

Atlan please comment on the situation. Maybe it would be better/easier to leave the versions FW FPGA AL3 0x15yy, FW FPGA EF2L 0x16yy, FW FPGA OEM 0x14yy?Thanks

[Felipe Lacerda]

Hi,

FW for FPGA AL3,EF2L and EP4 are not the same.

The latest released FW for FPGA AL3 is version 0x1532 and works only up to FW DSO 1.00o8.

For FW DSO 1.00p0 or FW DSO 1.00p1 you need FW FPGA EF2L 0x2000 or FW FPGA AL3 0x3000 or FW FPGA EP4 0x4000. Version 0x1yyy means OEM FNIRSI.

Atlan only posted FW FPGA EF2L 0x2000 to the forum for testing. (Atlan generated FW DSO 1.00p0-1 so that I could test the new FW FPGA EF2L 0x2001).

If you install FW DSO 1.00p0 or FW DSO 1.00p1 and leave the old FW FPGA AL3 0x1532 or the old FW FPGA EF2L 0x1632, your oscilloscope will not work.

I understand that changing the FW FPGA numbering causes problems/misunderstandings for users. Sorry

Atlan please comment on the situation. Maybe it would be better/easier to leave the versions FW FPGA AL3 0x15yy, FW FPGA EF2L 0x16yy, FW FPGA OEM 0x14yy?Thanks

Hi, thanks for the explanation!

I also updated to the DSO p1 version with the Atlan AL3 firmware (0x1532).
[EDIT]
Downgrading to version o8 worked using the Updater software itself.

[dougduck]

Downgrading to version o8 worked using the Updater software itself.

Thank you Felipe Lacerda

[ObsoleteDIY]

Hi,

I am attaching a comparison video of EF2L FW 0x1600 and FW 0x1601. It's a small difference, but maybe less hopping at 100kHz / 400ns pulse?

https://drive.google.com/file/d/1txvy-bqILvfMLbsdvJpm9_CGVEK_nUjp/view?usp=sharing

use FW1.00p1 and dots mode for ch1, linear skipping samples!

Give me the modified code so I can see it on the pages right away and not have to download and open the file. Just make the changes related to what you mean by channel A+B

Basically, it was done so that the trigger level was compared only on channel A (which is inconvenient because there is a lower probability of capturing the trigger - i.e. more samples must be taken to hit the trigger)

The FPGA handles all of this. The DSO firmware doesn't handle this - it just sends the trigger value at which it wants the capture to occur.

Hi Atlan,

I finished testing FW DSO 1.00p1 + FPGA EF2L FW 0x2001 and I’m sending a video link.

https://drive.google.com/file/d/1ucWUfSq_xf5YccifePLng9IJYW4LbbsF/view?usp=sharing

In DOT mode for CH1, the waveform looks better (no jumping). The trigger position is inconsistent — sometimes it moves across the whole screen, sometimes only a little. I had the Trigger position set to “MIN”(Would more pre-trigger samples help, or is it another issue?).

I tested Triger - Auto, Normal, and SINGLE modes — everything seems to work. In SINGLE mode, the screen does not clear while waiting. It’s not a bug — I’m just used to other oscilloscopes where the screen clears.

My final test file zaklad.v is attached.

[Atlan]

When I have time, I will modify the program to ensure that the trigger cursor position is recalculated when the time base changes. I can also add deletion in single mode.

[Atlan]

It should work. You have to test it, I'm glad that I can get to someone now.
Added recalculation of the trigger pointer position H. Added dynamic pointer in the lower part. (its size changes depending on the number of samples...)

I didn't get to test your version of FPGA firmware, nor do I have it installed. (The reason is simple - if there are any errors, it will cause incomprehensible errors that are not related to the DSO code) so that I don't forget, I don't know if the number of samples for EF2-8191 and AL3 6143 was switched in the last version (so that it doesn't cause you a headache.) it is now fixed

DSO FW "v1.00p2" //clear scren on single and other trigger mode, change calculation trigger marker, fix calculation EF2 and AL3

and NEW picture for scope big change scope.bmp

[Atlan]

v1.00p6 block move trigger level on waveform mode,fine tune horizontal position

[Etrius]

Can I use it on AL3 FPGA?

[Atlan]

FPGA fw 2002 (2xxx EF2 family, x002-version 2) previously in the package was version 2000, both work with 1.00p7

fw 2002 is a bit unstable

AL3 NO, I don't have a ''zaklad'' for fw 2002 and we are working on it

[Atlan]

Can I use it on AL3 FPGA?

without any guarantee it should be 2001, for AL3 but with a limit of 12000 samples

untested, I don't mind

[Atlan]

1.00p8

[Etrius]

without any guarantee it should be 2001, for AL3 but with a limit of 12000 samples
untested, I don't mind

I'll try it now and let you know...

[Etrius]

I tested the AL3 firmware with software version 1.00p8. Aside from the diagnostics page, which correctly reports version 2001 with 12,000 samples, it says EF2-L45. You probably forgot something...
I ran a few simple tests, and I'd say it's basically functional. I displayed square and sine waves and the code generated by a remote control to check the sampling depth. I had no problems. However, I noticed that when the acquisition rate switches to 200 MSa/s, the software seems to freeze, as does the acquisition. Basically, it doesn't work. Furthermore, high-speed acquisitions are noisy and jagged. You could probably consider displaying a moving average.
The product could be improved, but I'm still satisfied with the work you've done, and I thank everyone.

[Etrius]

I just noticed that I can enable moving average mode. Great!!!

[Atlan]

The firmware is for EF2 with 12000 samples, so that the DSO uses the correct memory access, it needs to think that it is using EF2 and not AL3. The difference between EF2 and AL3 is basically the size of the sample memory.

We know about the trigger and signal jumping, we are working on it.

[ObsoleteDIY]

Hi Atlan,

I made various modifications to the FW FPGA EF2L. Version FW FPGA EF2L 0x2008 seems to work better. Please check and test it.Thanks

This version FW FPGA EF2L 0x2008 is similar to version 0x2001 = dual channel trigger, but the trigger level has been adjusted based on the edge (eighth attempt to eliminate noise in the trigger ). I changed the trigger arming from 4 samples to 1 sample (a weak solution, but it allows the trigger to react to narrow pulses).

NOTE: I am working on a new version of FPGA FW EF2L 0x2009. I am trying to make the trigger compare all combinations of AB BA samples. I don't know if this change will improve the stability of the triggers.

[Felipe Lacerda]

Can I use it on AL3 FPGA?

without any guarantee it should be 2001, for AL3 but with a limit of 12000 samples

untested, I don't mind

feedback with this version of the AL3 FPGA.
Artifacts on 100M, 200M freeze.