Optical Bench REDUX: Digital Switching can have Analog Functions!

[RJSV]

   Implementing a FOR-NEXT LOOP is holy grail in passive computational structures.  One helpful method is using the 'unraveled' loop code analogy.  But even the decrement and test is only partially obtained, where the individual BUS line shift-overs used as substitutes for (active logic) decrements are the first part of any conventional looking FOR-NEXT.  It's the active test for zero, or for some other end point, that's the problem.
   One possible solution is to let the (unrolled) loop repeat regardless, or unconditionally, and exert control on a parameter, like the For-Next step; decimating on each iteration, until it's just an 'empty' set of operations.  That could be, for example, a parameter that ends up zero, added to the light beam, ...effectively being that the loop functions are expired, even though the unconditional loop keeps circulating.
   A design could utilize small mirrors, for having one column, 'folded' over itself for compactness, but that extends the effective length.  I'm thinking, 15 cm long each, and with perhaps 20 runs like that. Something like 100 individual 'loop' like iterations could be done that way, but please note THIS AIN'T a micro-scale!

[RJSV]

   The program step manipulation in any FOR-NEXT loop is the stickler, as there really is no program step address (register), it's all just physical progress through each series item, in turn.  Any other, separate function would be integrated with the FOR NEXT structure (just described), as a serial series of 'stacked' lines of elements, stacked or folded, for packaging convienince.

   What's going to be super-helpful is obtaining some expertise on a Solely Optical output function.  If some physical output or device can receive  control while skipping any electronics AtoD then that makes for some real speed / power savings.

[RJSV]

   It's really a challenge, to attempt as close to an integer decrement as possible.  Certainly, with the multiplier in this suggested style of analog 'stamps', with the multiplier being digital as a discrete integer, I.E. whole, discreet quantities of the Multiplicand are transfered.
   Then, you have the multiplicand, a wide open analog quantity.  Exploration of substituting the modifying function that IS possible, (vs. integer decrement), one choice could be:
   Multiply by 8/10: The downward steps would be:
   { 9, 7.2, 5.76, 4.608...} which could be considered as too little, compared with goal, to closely look like an integer decrement; { 9, 8, 7, 6, etc.}.
  Using multiply by 9/10 each, the sequence w/be:
   { 9, 8.1, 7.29, 6.561, 5.90} which you can see, gets down to '5.9' whereas a straight integer decrement would get you down to 5.0 (integer).  So, that choice of
   ÷10 and X9  could be deemed as 'too much', while the former choice of ÷10 and X8 could be deemed as 'too little' of an approximation, of integer count-down.

   All this is fascinating and confusing territory, and at the same time !

   In order to do a finer multiply, could next try X.85, remembering it's DISCRETE, not analog.  So, you need a scale using 2 decimal digits. That would be an apparatus having 100 'flaps', closing 15 of them to get that 0.85 ratio.
I'll have to work out those numbers, but point is, trying to get best closest match, as substitute function for the discrete subtraction, of each 'i' step in a FOR-NEXT
structure (unwound loop).  You still won't be able to use that 'step' parameter directly in integer form, such as to read 'memory' at $4010 + 'i' offset.  Discrete means all or nothing, of the multiplicand copies stamped out.
   Of course, any 'copy' of the light beam amplitude is made by splitting the beam, proportionally, and downgrading the 'value' scale. So, for example, having a beam at 100 lumens, split in two, the 'new' standard full signal would be downgraded to 50 lumens, that being the case for either new 'sub-beam' , as they proceed on their way, into next appropriate passive logic section.

[RJSV]

There are two ways for this to happen;
   One method, discrete rightward BUS shifting,  eventually emptying to the BUS lanes, after 10 rightward shifts, each individual shift will drop one signal beam.
   Method #2 using ratiometric reduction, could result in a classic infinite sequence, like for example, a divide by two (that's done by ÷10 with X5, for X 5/10).
That infinite sequence never gets to zero, but a ratio reduced series like; {0.5, 0.25, 0.125, 0.0625...etc.} could get down where it's essentially 'done', or so negligable amount as to be harmless, (as the loop keeps trudging on ...and on)
You might have the device execute 2000 'loop equivalents',  at a fast 200 pico-seconds each, but with only the first 100 repetitions matter, as doing anything.  That way, at finish, get similar action results, as compared with a classic 'FOR NEXT'.

Confusion dept. 483, floor 13
Thanks,
Rick-Jack

[RJSV]

   Here is a good referral;
YouTube University of Illinois Nanophotonics (1hr:08)
  That lecture Professor is very listenable and clear, including slow repeats when summerizing difficult parts.  Mentions refractive index and other optics from EE perspective, and bio-sciences perspective.
Site search says something, about 'Nano-Bio Node' ?

[RJSV]

   This latest diagram really sets the stage, for presenting the essence of my title,. involving data transfer, in novel ways;

   "...has both Analog and Digital aspects and functions..."

   The 'confusion' in the picture is somewhat deliberate.
Notice; the two BUS formats illustrated, inside that big blue circle, have a look that is, well..., identical.
The digital and the analog characteristics are equally expressed.  For the 'digital', I figured using basic signal from 0 to 1 volts (0.999 max.) and with the comparator level using 0.5 V, to signal a digital 'ONEs' state, similar to TTL thresholds.
   Of course that's the voltage equivalent for any light intensity discussion.  A glance at the BUS representations, there, inside the blue highlighting circle, shows the 'compartmentalized' version is re-drawn, as a distributed set, once for the digital set, to be used in fully digital settings, conventionally, and the same '5' value is also expressed, drawn as the analog word, in a special form, of right-justified fill.
Either of those BUS formats can almost be used interchangeably, with some care.
   There's still some conflict, as I would tend to limit that '5' value shown, to more like '0.5' in actuality.
It's the 'zero' value handeling that's not resolved here
Notice sometimes the BUS lanes or columns are
 1 thru 10, sometimes 0 thru 9...But it's all eventually going to be structured consistently.  Notice, while reading some of the methodology for BUS encoding, that the 'Multiplicand'  gets split into 10 pieces, one of which doesn't ever get used, at least not in a decimal multiply, using up to '9' separate additions.  You can see the hints on that, down at diagram bottom, where it is showing the Multiplicand after analog weights have been re-distributed, in preparation for the multiply function to do the conditional additions, for each column,.in that decimal BUS.
   Ironically, the most conventional looking BUS format, ((please see the positional weighted word, 4th down from top of illustration), is the least useful!

[RJSV]

   For more clarity, and to correct error, the light beam amplitude, '5', was supposed to be split up, 10% into each separated path, (last diagram incorrectly showed that 5 ÷ 10 as being 0.2 for each confined path or conduit).  One aspect, the full diffuser, I have not yet detailed.
   Diffuser action creates a smoothly distributed amount of light going down the machine column.  Starting from top (electronic light emitters, like LEDs), will drive the proper columns.  Another permitted input set could also be one of the 'right justified fill' BUS format styles...let's just assume a previously acting processing element has produced 'answer = 5' and is sending it into our diffusing 'cone', shown in schetch.
First, the internally reflective cone mixes everything, so each individual signal gets all merged.
Now, being 'bosons', that type doesn't react or repel each other (each beam).
   Once mixed and compressed, in the reflective cone's neck-down, the whole beam is re-enlarged and sent on the way, into the 10 conduit channel, shown at bottom of diagram.  Also, not shown is various light diffusing or 'milky white' plastic or glass diffuser(s).  Trivial to describe, but that even light intensity is a crucial aspect, of the 'Conditional Adder' function, for best accuracy and repeatability.
   You can also imagine, many types of optical BUS feeds can alternate with this specific right-justified fill, as long as total '5' gets mixed down, into cone neck for re-distribution.
   With a 3X multiplication, you've gotten 3 columns of light, each being a 10% portion, and so with result being conditional adding, on each of the 3 enabled columns.  The actual gating of the light, via LCD element, is being called a 'flap' or light flap.
   Result, for the 3 X 5 = 15 multiplication,  comes out, at bottom of diagram, as a '1.5' which can be used accordingly, assumed to be simply expressed in fractional form, but you've still got a  useful multiply.

[RJSV]

   I'm asking if someone can answer question about generic Multiply-Accumulate coding forms, (although much of that info is published in YouTube lectures etc).
The trial and error test 'code' or sequence model would be along the lines of 8-bit integer multiplies that get summed...along the methodology of convolution.
Likely, that could be 16 bit binary accumulation, having each element summed being an 8 by 8 bit Signed multiply...That's the big-picture model, for the do-over in optical logic arrangements.  Performing Convolution is the speed-up custom accelerator's main purpose.
   So, that means optimizing the generic FOR-NEXT structures, and focus on convolution, of, say 200 by 200 elements in moderate resolution imaging.
Meanwhile, of course, plenty of course material out there.
   YouTube, heavily accented and hastily delivered technical jargon, could use improvement, as truly near-impossible to 'grasp' what the guy is even saying...never mind a difficult math-heavy topic to start with.
Often, I can't continue watching (deciphering) some heavy physics discussion, might be best to stick to native tongue...let some others translate.
In those cases, I often think "...Smart guy...I'm not sitting thru this marble-mouthed lecture..."

[RJSV]

   My idea for a fast switch exploits a blocking or denial of the re-emission widely known, in outer shell electrons...a statistical 'cloud' of probability, if I got that right.  The process is to pump in (photons), essentially saturating the absorption.  But, alas, perhaps
 re-emission occur still.
I'm thinking, maybe there is a delay,
900 Femto-seconds, before re-emission grow, on the extreme start of bell curve.
That means another beam and path could get disrupted, during that tiny window, before absorbtion and re-emission repetitive actions.  I had noticed, from Colleqeum lecture concerning 'refractive index', being associated with uptake-re-emit dynamics.
   The affected beam, would be at extreme folded or flattened 'X' shape.  'Leaky Gate' means that contraption still leaks to output, to negligable effect.
   Another possibly needed component might be heavy use of timing (square shaped waveforms).  That way, the regular setting, with all the re-emissions, would not be during a short, regular window.

[RJSV]

   One limited use Subtraction is one case where mods to the light beam, or actually modified copies, are made.  An un-signed value comparison, on the BUS type shown, (a couple figures back), it's taking the rt. justified, filled word and, 1 for 1, having an active gate close anywhere that column has a '1' to subtract.  Actually, this case is more like digital 'AND logical'.
   End result the output word has 4 places with '1', and so has implemented 7 - 3 = 4.
Taking it graphically helps, and also note that the output isn't rt. justified, so going from there won't be in the format, for column-identifed usability of the rt. justified and filled BUS word form.
   The optical logic is somewhat 'negative logic' in that the logical AND is done via an equiv negative input OR.
A tiny time window, 800 Femto-seconds, is supplied periodically, and unconditionally, and that low-going light pulse allows for a trigger situation.  It is during that and during the absence of clock signal 'ON', that a low going inverter input would cause a short dark period, to inverter input(s).  That then gives rise to a positive going inverter output pulse.

[RJSV]

   A brief glimpse at the higher speed switch, it is active but not with power supply, but has device delay.
The thing does a pump up of absorption, in that central region, with (only) an aside to the material. Thinking crystal embedded CO2 or silicon, but having usable bell curve, for the resumption if spontaneous emissions, in any quantity.
   The partial diagram shows the 'CONTROL' beam enters from lower right, and causes saturation, at the center of the big 'X' shaped switch.  Then, with or without good timing, the upright beam is the re-emission, from the original control beam at the different angle.
   Drop the control beam, and there could be a bit of a window, before the spontaneous re-emissions build up to normal statistical equilibrium...whatever that means in detail.
   Lower curve is simply an extreme shirt time after cessation of the saturating control signal ...implying a very short time interval.

[RJSV]

   In the full view, the optical switch has signal 'B.' (please see diagram), where the output contains both the original beam signal, and plus it contains a mix of the re-emtted light from electrons (effect).  I'm speculating a more encircularing pattern for re-emissions, maybe also going 'backwards, up the control conduits. (?...).
   The real time curve shows a brief dip in output, that would then go, side by side, with some static or slow variable.  When the 'A.' dip occurs, then the static (input) device will influence the 'circuit'...taking the place of the light emitting 'clock'.
So, when clock output 'falters', for 800 Femto seconds (10 - 15 seconds), if the other input is 'ON' the logical OR of the 2 beams, will not signal anything...Is when the slow or static 'B' input is 'OFF' that the 'negative true signal happens.

[RJSV]

   Oops, sorry I was a little sloppy / inaccurate there:
The 'A' input is an always there, periodic pulse, very fast, but avoids having to control it.  That clock signal generation is a story in itself, (120 Thz with 800 FS
or 0.800 pico-Seconds.)
  Input 'B' is the beam you want to affect; the main aspect is the inverting effect, that gives ability to implement various logic.  For easy example is the 'disruptive' effect being described, at the very start of the re-emission build-up, but a 'conditional' disruption, so that some, if crude, control is gained.


   

[RJSV]

   Here are some more 'napkin notes', concerning the art of simple subtraction.  And please note; the 'un-signed integer subtraction omits about half the range, stopping at '0'.  But, some signal proc functions want that.
   To do a subtract, '56 minus 8':
   Sounds maybe silly, but;
   Doing Minus 1, 8 times,
   56 minus (56/56) = 55,
  Or, 56 - (56 X 0.0178) ...ahem.

   Then, another round :
   To do '55' - 1 is minus (55/55)
   Or - (55 X 0.0181)...

And, next round will be;
   - ( 54 X 0.0185)...
Etc etc, until 8 of those happen.
That, naturally, would be slightly off, from pure digital results, but getting accuracy is the challenge.

[RJSV]

   Graph shows the ratio substitute for doing (perfect) digital subtraction.  The integer subtraction would be nice but you literally don't know what's there.  Owing to the fact that each real number, or a 2 digit digital set, has a count that varies in proportion to size, you cannot predict the exact size, for example, to subtract from '50' by way of ratio multiplying, vs size reduction to '30'.  In those cases, when using RATIO = .8 the 50 value goes, exactly correct, to =40.  The '30' with same ratio, .8, goes to =24, which is high by 4 counts.
The curve matching trials work good at ratio =0.8 X or at ratio of 0.7 for better low end match-up with ideal. That has bigger error percentage but in the bigger size numbers, range 80 to 99.
   The result is very similar to integer decrement, although with analog values, or real number smooth.

[RJSV]

   I'm pleased to see a way to decrement, as near to integer style as possible, and using simple ratiometric (multiply by 0. that's multiply by zero point eight.
Why can't text entry show that, without emojis ?

method. Each time in turn, a decrement is done, on the integer subtrahend (to be subtracted) and, one for one 'subtraction' from the minuend, to obtain answer.
It helps, to assume EVERY number digit, for subtraction, is '5' (not entirely true, lol).  In this example (please see diagram), I've tried to left-right 'FLIP' the word for taking off from the top end (left side of number) to see if that tactic helps the answer word format, that is, if the ending format can be 'right justified' filled, (it does, but only for the case of minuend being a '9'...others don't work).
   The procedure, assuming subtrahend in proper, right justified filled, is to diminish the subtrahend by way of physically shifting (to the right), while diminishing the minuend coresponding column, usually doing that via masking as logical (bit-wise) AND digital.
   It's very analogous to the previously described multiply actions, where the 'mask' indicated places to conditional add.

[RJSV]

   The idea behind the high speed switch is to create a timing of the statistical delay, of emissions.  That's a pain in the ass!  With a (first) timed event, such as pulse firing a laser LED, I'm thinking that would depend on INPUT, light, and would be timed for a bit later, while the device, or excited/depleted atoms is suppressed. That might only be 900 Femto-seconds!
   This way, feeding a non-conditional clock, negative logic, any 'conditional' input state, on or off, would be inverted, in a sense, (not statically).
If, clock arrives, falling edge, and that saturating or statistically delayed signal is also low, that can trigger the following logical AND stage.

[RJSV]

   The input must be equisitely timed, and lands in a window.  That input gating is a chore for subsystem design.  Would need a short window, 800 femto-sec. that is issued periodically, as a clock.
Any resulting short light impulse, would, usually be low going or a brief pause.
When the two signals are merged, the path would be of content of regular clock, (very brief), and an inverted pulse, or short low-going.  That's, in total still dark or '0' so the gate output does not get 'disrupted'.   Outputs operate, as the incoming pulse, is negative logic AND.
   Then, for a positive pulse light output, just simply send to a next inverter.

[RJSV]

   The diagram is not completely right, but shows the so-called 'Clocked Inverter'... or synchronous pick-up.
Input being active, that's a '1' encoded. Then, that light input flow abruptly stopping; I'm hoping that the device, a light pumped laser, similar to LED type, see 2nd waveform.
   The 2nd wave is statistical time to 'mean' recovery, of the very brief stoppage.  That's on order of
1200 Femto-seconds, at 10 to -15.  Third graph, lower, is the 'Inverted' pulse output.

[MK14]

!  !  !  !  !  !  !  !  !  !  !  !  !
My earlier post, seemed to get missed.
So I put this in, to make it more likely to get noticed.
Sorry . . . . ...          
!  !  !  !  !  !  !  !  !  !  !  !  !

   The diagram is not completely right, but shows the so-called 'Clocked Inverter'... or synchronous pick-up.
Input being active, that's a '1' encoded. Then, that light input flow abruptly stopping; I'm hoping that the device, a light pumped laser, similar to LED type, see 2nd waveform.
   The 2nd wave is statistical time to 'mean' recovery, of the very brief stoppage.  That's on order of
1200 Femto-seconds, at 10 to -15.  Third graph, lower, is the 'Inverted' pulse output.

Given that modern chips, can have billions of transistors on them, operating at rather high speeds, and then produced in mass production, for sale at reasonable prices.

Or even 5.3 Trillion Transistors!           

See here:

Micron's 2 terabyte (3D-stacked) 16-die, 232-layer V-NAND flash memory chip, with 5.3 trillion floating-gate MOSFETs (3 bits per transistor).

Source:
https://en.wikipedia.org/wiki/Transistor_count


How can a light based logic system, made out of individual components, such as laser sources.  Attempt to compete with that.

E.g. You make your device, with 5 transistor like, light gate things.

But these latest chips, can have 5.3 Trillion transistors.

So, a ratio of a Trillion to 1, which is mindbogglingly difficult to comprehend.

[RJSV]

   Here's a glimpse of a 'code loop', or what you might see with Basic.  Thanks, Mk14, folks are saying they want, some semblance to existing processing, but mostly, like you say, at massively small scales.

   The optical For-Next structure would start at 2000 loops, however that would be done in 50 runs, at 40 code steps each run.  That's considered 'vertical', downward, just a convention, while a recirculating path going upward is, again, more just conveinient language to describe circulation.
   It's whimsical, but wondering if a short light impulse could be shorter than the stack or code stack.
Each 'for-next run would decrement the loop count, but only that one time.  Using the active fast gate...
   The right hand side of circulation diagram has upward paths, of each BUS element, as possibly undergoing a simple amplification stage, for recirculation maintainance.

[RJSV]

   I was figuring 300 pico-seconds per frame...that is per 10 cm.
   But that includes '40' structures, vertically, so it's more close to 300/40 = 7.5 pico-seconds per processing element (path).  That could be something like 'X - 201' in that case having maybe an 'X' and a 'Y' register,...all starting to look like a simple programmable processor.
   Standardized full size would be '000' thru '999' with various decimal pt. locations.  One problem, with using such primative logic, is the BUS amplitude issue, when any computational outcome involves more weight.
Take, for example, '2 minus 4 = 8' as a low digit generator, needing 8 places having '1' or digital 'ON'.
That issue has solutions, rather unpleasant.
   The For-Next example, there is no explicit PC or line number, it is by location.  An example would be doing 3 different things, repeating during the 40 code steps or loop pass.
   One function is the usual decrement and test, at end of loop downward pass.  That is a 2 digit number, decrementing, while handling any of the underflow 'borrow' type signal, to the next higher digit.  So, 50 loops to start, then each bottom of pass will decrement using fairly simple shift right, but the underflow, borrow is the hassle.
   A second function example, would be a generator, that calculates 'triangular numbers', up to 15, where each is added, rather than factorial style multiply.
Each result then added, into the 'X' number virtual register (light path column).
   Then, example 3, the optical 'code' stack or list, could input some sensor, gated to virtual register 'Y'.
Each of these heavy pathed BUS sets are 10 wide,...so miniaturizing might be the ONLY way.
An example processing, on the sensor, say at 2 digits or '00' thru '99', could pre-process by multiply the immediate sensor input by (digital) set value(s).
All very fast, if maybe sloppy.
   Each if those 3 examples would be interleaved into the 40 available slots, so maybe flexible assignments could be 'coded' which just means slang for building that particular function step, in reflective or other elements, for example.

[RJSV]

   Please excuse the numbers, but comes up to
  12, 500, 000 individual BUS paths...Any questions ?
   Some recent matrix organization is going upwards, from 100 by 100.  So suggested is (250 X 250), which is about 62 K or 62,500.
That's close, also, to binary (256 X 256).
So, with 4 registers, each having 3 digits X 10 lines or paths, it gets up there; 140 individual optical paths when you've also included a loop iteration counter.
So, the figure is 62 thousand processing BUS elements times 140 getting 8 or 9 million,...headed to 12 M soon!

   Not actually that intimidating, when I read some Quadrillion nerve related connecting elements ...which sounds farcical, in the face of it, but apparently the biological systems account for huge numbers of functioning connective elements.

[RJSV]

(Please see attached diagram),. The 100 data lines, or paths aren't so bad when organized square. The 10 by ten square naturally holds 10 data BUS sets
Diagram shows highlight on the 'B' register, Low, or 'BL' for short ID of the digit.
 

[RJSV]

   Looks maybe odd, at first, but this next diagram features a 'code step'...really a 'load value' type instruction, although not some code step you could type in.  In Basic, that might be 'Let BL = 3' or for microprocessor might be transfer from elsewhere in the little processing sub-unit.
   The light wave conduits block the 'old' BUS value, completely, then substitute the new constant value, into the flow, so to speak, or the 'virtual BUS'.