FPGA

Failed reading data from DDR4

Pruning bits in digital downconverter (DDC)

VHDL CODE QUESTION

Programming with Topjtag trought blacfin only

Is my petalinux image too big?

Xil_Out32 causes my program to crash?

FPGA Bluetooth/WiFi Project

Verilog best way to replicate if else logic inside always block? Macros?

Lattice FPGA programmer

Design cascaded sinc filters, how to?

DDR3L -> DDR3 compatibility

Detection of damaged pins of FPGA - CYCLONE V - 5CSEBA2U23I7SN

AMD/Xilinx announced Spartan UltraScale+ family

MIPI RX low frequency

Newbie DRAM interfacing questions

Altera is back

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Problems with Quartus Modelsim simulation

Seeking Book and Library Recommendations for FPGA Networking Projects

Guide: Getting Xilinx ISE to work with Windows 8 / Windows 10 (64-bit)

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Synchronized SPI communication between three FPGAs using VHDL

Bram Memory Size Configuration

OpenHBMC. Open-source AXI4-based HyperBus memory controller

Gating the clock

ice40 ultra icecube2 software does not recognize my input constraint

Simulating Memory in verilog

Cyclone III EPC4 flash - programming off board

FPGA to softcore or hardcore data stream bus

Phase sync two same frequency input's ?

ice40 Hx8K project not configuring from external flash

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$20 FPGA board with 2x8 PCIe and 2x QSFP

FPGA based SSDs

Jtag with Wiggler

Indexed pins in constraints file?

How to simulate/testbench with IceStudio?

DE10-Lite Problems with 7-Segment Display

Original SiLego Mixed Signal FPGA Legacy- Old Software?

Comparing performance of genuine vs cloned programmers for Intel/Altera FPGAs

Best replacement for AMD/Xilinx CPLDs XC9500

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VHDL Port Declaration issues in Lattice Diamond