FPGA

Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...

Best value for money FPGA board with Xilinx Zynq-7000 All Programmable SoC

FPGA Xilinx XC3S400A

Xilinx SDSoC development environment - is it free or how much does it cost?

FS: Altera FPGA - Arria II GX EP2AGX45DF25I5N

Altera Quartus - please help a novice to make timing simulations

FS: Digilent Atlys Xilinx Spartan 6 LX45 development board (UK)

Altera Max10 FPGAs

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Altera A-C2FB kit ( board documentation )

FS: FPGA dev kit: Altera Nios II Embedded Evaluation Kit, Cyclone III Edition

Xilinx deveelpment kts

Xilinx Development Kits

Xilinx ISim: Display I2C as hex in simulations?

Vintage Altera

An open source Xilinx Spartan 6 miniPCIe development board

Review and repair of ALTERA Arria II GX FPGA Development Kit (DK-DEV-2AGX125N)

Intel to Purchase Altera?

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Automated tests with Xilinx ISIM on windows

An open source Xilinx Spartan 6 miniPCIe development board

FPGA implementation with Xilinx chips

Altera blaster good deal ?

Altera Quartus II ROM megafunction?

What is this for --> XILINX FPGA development board

Xilinx now offically supports their virtual cable driver!

Help with Altera Cyclone III configuration problems.

Altera ModelSim Starter edition license error

For Sale (UK): Xilinx Platform Cable USB II

Net "clk50" not found - only after adding extra "process" block (VHDL, Xilinx)

Xilinx ISE -- Coregen DDR Controller IP problem -- Spartan 3e

Deeds a Digital simulation suite (and VHDL Generator) Altera QII

Altera's shenanigans with a state machine, or me failing at verilog?

US and Canada only. Win a Digilent Zybo dev board for the Xilinx Zynq 7000.

How to read contents of a Xilinx ISE bit file

Altera MAX V vs MAX II. Any substantial reason to ever consider the Max II?

Error about library path of Simulation Waveform Editor of Altera Quartus II

Xilinx FPGA bitstream

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Enpirion/altera switching regulator problems

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Bought an Altera CPLD dev board, where to start?

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Does anyone know how many times an Altera MAX II CPLD can be reprogrammed?

FPGA EEVBlog segments / Xilinx buyer's remorse

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