"NU180" - A U180 drop-in replacement for the 3458A.

[Zondar]

Yes, look at GND2 as well.

Like all supplies, there are, or should be, 10+ uF capacitors at Vdd2 and GND2 on the boards, as well as 0.1 uF at every Vdd2 and GND2 pin. Considering that only the switches will be using these, and that they use rather little power, this should be OK.

If you have ferrite beads or resistors or any other impedance in the path of any of these (Vdd1 as well), then consider shorting them to rule them out as causing any dips, etc.

Edit: I see you are using 10 Ohms in series with Vdd1 and Vdd2, as well as in series with power in other places. In combination with the 100 nF you are using gives you a 1 microsecond time constant on those. You even appear to be doubling this up in places, i.e. series 10 Ohms and 100 nF globally, then another series 10 Ohms and 100 nF locally. I know people sometimes put a small resistance (e.g. 1 Ohm or so) in series with power for the sake of power filtering, but it could partially explain why that supply is changing depending on load.

Also, while 100 nF is far from nothing and it's probably OK, it's not 10+ uF (as most boards use) either. You should probably use more like 10-47 uF for general decoupling at NU180's power input (and GND2) pins, and smaller ones locally very close to each IC's power pin and GND2 connection.

Also, I see that you are using pull-downs after the flip-flops. Why? The point of the flip-flops is to eliminate the need for this. They will not help here and if anything will only do harm, like causing nearly 1 mW of power consumption by each one, and a corresponding sag in V_OH, when high. You should remove them, in my opinion.

Also, I'd doubt that GPIB itself is causing a problem. When GPIB is used, I would presume that there is a pause in ADC conversion(s) while it's reading out. So I'd rather suspect that the issue is a change from near-continuous conversions to conversion-pause-conversion-pause, etc.. I would wonder about any time-constants involved somewhere that allow shifts based on these duty-cycle changes (e.g. like the RC noted above). I'd also wonder if that sort of explanation could extend to the NPLC # issue, as the two sound rather similar in ways.

(Also, I see that "mod in" is still going to a digital input pin, which does not correspond at all to how U180 handles this, but I've asked for a rationalization for that enough times now....)

[hanzhu]

All pull-down resistors are unused.

The following are today's measurement data of U180 and NU180. The operating current of each pin is obtained by measuring the voltage across a 1-ohm resistor.
NU180 VDD1 CPLD inverter flip-flop: 28mA
U180
VDD1   3.78mV = 3.78mA
VDD2   0.08mV = 80μA
MOD-IN1   0.006mv = 6μA
MOD-SENSE1   0.005mV = 5μA

The measurement shows that the operating current of NU180 is ten times higher than that of U180.

[DB4UCH]

NU180 VDD1 CPLD inverter flip-flop: 28mA

I also measured the current on VDD1 of my NU180 v0.4.2 and I got a value of 29-30mA (I have two FFs so the slightly higher current tracks)

Another thing: The inguard 5V supply shows quite some variance during operation (a dip of >300µV during the pause between integrations and an increase of >200µV while the integration is halted). No difference was observable between different NPLCs / GPIB operation other than the obvious increase in pluses for lower NPLCs.
I attached two plots below, both taken using a 34401A @ 1 NPLC AZ On. The 3458A was measuring a short @ 100 NPLCs in the 10 DCV Range.

Greetings,
Simon

[wanghar]

2.由于没有 wanghar 的 V0.71 版本 PLD 文件我自己按照 wanghar 图纸和 MiDi 文件进行了编写测试，同样发现V7版本开机出现 202 错误。我没能通过修改 PLD 文件消除 202 错误，用 V9 版本可以正常测量。希望wanghar把 V0.71 版本 PLD 文件发布出来进行一下参考。

Without access to Wanghar’s V0.71 PLD files, I wrote and tested codes based on his schematics and MiDi files. Error 202 still pops up on startup with V7 firmware, which cannot be eliminated via PLD revision. Measurements work properly under V9 firmware. It would be appreciated if Wanghar could release the V0.71 PLD files for reference.
 

I've tested two 3458As with NU180, both running firmware version 9.2. My guess is that all my NU180 revisions would likely also throw error 202 on version 7.2. Attached are the CPLD code  for the V0.71 PCB.

[Zondar]

This is all very interesting!

Vdd2 should show rather little current draw, but since it's generated from Vdd1 via a diode drop, when Vdd1 is shifting around, Vdd2 will follow along as well.

If it's not too inconvenient, can the power consumption of NU180 be monitored while in operation so we can compare it to the voltage changes? This might help separate whether the rising and falling voltage on Vdd1 (and by inference Vdd2) is due to NU180 (I suspect not at this point) or something else.

It's not unexpected that NU180 uses more power than U180. Most of the power is used by the CPLD - in particular, about 23 mA of static consumption - which I don't think can be reduced (and this is the last one in production that is 5V compatible). The rest will be semi-static power used by any pull-downs, and dynamic power consumption due to clocking, etc.

Possible fixes:

First, a few small things: The second FF, if used, can likely be dropped, saving a small amount (and reducing noise). Using 3.3V inverters and FF's instead of 5V will help a little. We preferably want the FF's and inverter to be purely CMOS, too, for zero DC consumption.

Next, a best guess at this point is that small fluctuations in supply voltage are finding themselves into the conversion process. I doubt that simply adding capacitance will fix it, but it can possibly be regulated out.

One possible quick test would be to temporarily use an external supply to power NU180's Vdd1 and/or Vdd2.

Then, the CPLD's spec allows the power supply to be as low as 4.75V (commercial grade) or 4.5V (industrial grade). So whether NU180 is responsible or not, an extra-low-dropout regulator with high PSRR could be used to regulate the on-board 5V to as close to 5V as possible, i.e. 4.5-4.75V, and run with that. If that's not workable, it would be messier, but a higher supply could be picked off elsewhere and regulated to 5V.

If it's fluctuations on Vdd2 that's responsible and not Vdd1, then that's easier: Simply regulate to anywhere around ~4.5V from Vdd1 and use that for Vdd2. (Note that GND2 is still a concern as well.)

[Zondar]

I've measured Vdd1 and Vdd2 as in Simon's recent post.

As expected, Vdd2 follows any DC changes in Vdd1.

First plot: Vdd1, continuous operation with NPLC=10, measuring 10V. The second half of each NPLC=10 acquisition, after the small upward spike, appears to have a slightly lower voltage.

Second plot: Vdd1, single NPLC=10 acquisition measuring 0V. The dip in the second half doesn't appear when measuring 0V (vs. 10V).

Third plot: Vdd2, single NPLC=10 acquisition measuring 0V.

Forth plot: Vdd2, continuous acquisition, NPLC=10, measuring -10V. A very slight upward offset is seen in the second half of each acquisition sequence.

When measuring 10V, the second half of each conversion sequence has a slight dip, whereas measuring -10V shows a very slight upward tendency. Neither much appears when measuring 0V. It's very small, but any comments?

[Kleinstein]

The slight change in VDD during the measurement cycle could be an issue. The 2nd half of the measurement should be the zero reading in the AZ cycle.

The main idea behind the AZ mode is that the ADC behaves the same for the measurement of the input and the zero. A different supply voltage for the 2 cases could effect the zero reading and this way cause an offset. If one just looks at the supply voltage changing with the input signal, this would be one way to create nonlinearity..

There remains the question on wether the change is more with VDD or the ground. The ADC produces some current to ground (the reference send to ground, when not send to the integrator, current from the slope amplifier), that has no compensation. This could cause a shift of the ground level.
I see no real reason why the supply current for VDD1/2 should change much with the input signal. So this could well be more a shift on the ground side.

The short, but quite large pulses up could also be an issue. Are these related to the data transfer ? The fiber optics driver consumes quite some current from the 5 V supply.

[Zondar]

Yes, I was wondering if those offsets are the result of, or cause of, some non-linearity or offset. The differences are so small that it seems unlikely, but the offsets/non-linearity are very small too.

If the second half is the AZ phase, then it's likely that the first half is being affected somehow rather than the second. That is, with +10, the first half is higher, and with -10V, the first half is lower.

The short "upward pulses" would actually be periods of less downward sag. The higher voltage would typically result from a lower load on the Vdd1 line. Presumably some math and result display occurs during that time (I was not using GPIB). I don't think they are an issue themselves.

It's not clear if this presumptive "changing load" is on NU180 or elsewhere on A3, etc. But if we can measure NU180's power consumption during operation, we may learn more. I also neglected to look at GND2, but will do so tomorrow.

I don't think my genuine U180 will allow my machine to work at all anymore, but it would be interesting to look at this sort of thing with a real one, too.

I believe Vdd2 is simply following a diode-drop below Vdd1. Given that, it should be possible to attach a power supply directly to that pin and pull it up slightly. The diode should stop conducting and let the power supply fully take over. Thus, at least Vdd2 should be stable, and perhaps something will be learned from that. I'll try that tomorrow too.

[Kleinstein]

The shift in the voltage is likely not just from load to VDD1 / VDD2. I see a good chance that part of it is from current to ground. So it can really matter where the gound is taken from.
One would likely see even larger ground shifts, if one looks at the voltage between ground on A1 and ground on A3.

The GPIB part is with the output side and thus should not effect the ADC. The part that can have an effect the the data tranfer from inguard to outguard. The fiber transmitter should run at some 20 mA. There is filtering for the fast part (individual bits), but this would not help on the longer scale.
There would be a little math before sending the data, but AFAIK the 8051 type µC should not change much in the consumption wether it is active or just waiting during conversion. The more serious math is with the 68K type CPU on the output side.

[Zondar]

The shift in the voltage is likely not just from load to VDD1 / VDD2. I see a good chance that part of it is from current to ground. So it can really matter where the gound is taken from.

As a reference ground, I was and am using GND1 right on the NU180. That is the "A" ground on A3. I'm unclear what other grounds would be pertinent to its performance or why. There is GND2 of course, but I wouldn't call that a "ground," it's really just a negative supply.

I noticed that my plots differ from Simon's. I do not see a dip between conversion periods.

I tried raising Vdd2 from its nominal ~4.3V to 4.5 or so with a power supply, which was not a problem. As expected, once the power supply took over, the dips, etc., were gone, and the output became flat.

I also raised Vdd1 slightly, which also worked OK (Vdd2 still tracks Vdd1 here). There is more like 150 mA used on that. This still looked like the above photos, just raised slightly. As I changed this voltage, the 3458A's output (measuring + or -10V) also changed, so this voltage is important for accuracy.

I also looked at GND2, and a photo is attached below (NPLC=10, 10V measured). It shows the same sort of dips, etc., as Vdd2. Power consumption is small (<2 mA). I pulled this down slightly with a power supply, and again the output became flat.

None of the above made any clear improvement, e.g. measuring +/-10V still resulted in a small offset between them. Because of the "dips", etc., we could contemplate further regulation on Nu180, but it's not yet clear that this will help. Perhaps others can play with these voltages too and see if they can discern an improvement, or else maybe point out a test I can do that would lend further evidence one way or another.

Update: I explored the sensitivity of the output based on changing Vdd1 and GND2. (On the board I am looking at, Vdd1 is used for the switches, so Vdd2 has no impact.) All measurements were with +10V as input.

* Changing Vdd1 did change the output. When changed by +0.1V, the digitized output changed by about -17 uV.

* Changing GND2 did change the output, initially. The first 0.1V lower (from about -0.6 to -0.7) changed the output by about +23 uV. This effect rapidly diminished, though. By the time GND2 reaches -1V, the output stabilizes, with no further changes in the digitized output. (I checked if the stabilization somehow fixed the polarity offset, but no.)

Unfortunately, I do not currently have a working board that uses Vdd2 for the switches, so I can't comment about its impact vs. Vdd1.

[DB4UCH]

A few things to note:
The power consumption of the NU180 seems to be constant during integration and increases slightly during pauses between integrations. The base current is noticeably higher for my NU180 now, (I did play around with the CPLD code, but I also seem to have killed my programmer, so I can't go back to the old code till the new one arrives to test this hypothesis) I attached plots below (taken with a 34401A in the 1A range, 0.1 NPLC) for 100 and 10 NPLCs. The NU180 was powered by a dedicated power supply, with the GND also being connected directly to the NU180 PCB.

I also tried to put a 7805 directly at the NU180 and to power it with 9V from a lab bench supply, but no real change in noise nor the zero-point issue was observed.

As for the NU180 VCC influencing the gain I measured an effect in the magnitude of ~0.2PPM / 1% of change in the 5V supply.

About the timing:
I tried to systematically compare the timing between the U180 and the NU180 and I noticed the following: The U180 takes about 55-56ns from the rising flank of the control signal to show a reaction at the integrator. Using a 74LVC1GU04GW as the inverter and a SN74LVTH574PWR for the FFs leads to a timing difference of ~4ns in comparison to the U180. The NU180 lags behind the U180 here. I attached two screenshots below showing this behavior.
This is about as good as it will get (without delaying the clock by nearly a whole clock period i.e. 46ns), as the 74LVC1GU04GW and SN74LVTH574PWR show about 2ns of delay and the control signals from the A3 lead by ~3.5ns in relation to the clock. (the CPLD takes about 3-5ns for the signals to propagate btw.) This leads to a delay of 32-35ns between the control signal from the A3 board and the switch control signal.

Various clock configs lead to an even worse timing difference. I wasn’t able to see a definitive trend related to the zero point here, so I do not think the timing is the issue here.

Greetings,
Simon

[Zondar]

Simon:

It's not clear to me that a constant, uniform, delay of ~4 ns, i.e. if the rising and falling edges are both delayed by the same amount, should have a negative impact. This just shifts everything uniformly to the right by ~4 ns. As long as that's much lower than the clock period to avoid collisions with other actions, it should make little difference.

What could be important is any differing latency of rising vs. falling edges. Quite often falling edges are faster than rising ones due to the difference in mobility between electrons and holes. Sometimes efforts are made to equalize these (e.g. the P-channel pull-ups are made larger to compensate), but often not. A difference in rise/fall times effectively leads to a difference in latency, even if there is no explicit extra delay.

In the case of SPDT switch-pairs, an asymmetry in rise/fall latency will (I think) cause one switch to be on longer than the other. This could very well cause a problem. Which pin(s) specifically have you been looking at?

About power consumption: You were presumably powering Vdd1 externally while the board was still loaded onto A3, but with that pin disconnected from A3? If it's disconnected, then Vdd2 will remain powered through the A3 board and will be unrelated to the voltage you apply to Vdd1. I'd suggest trying to change Vdd2 independently too, which is simple as it does not need to be disconnected from the A3 board (the diode will cut off and leave it floating if it's raised up a little, but I wouldn't lower it much).

Power consumption should rise as Vdd1 rises. But I can't figure out why the power consumption would increase while less work is being done. That is not normal, though it's an exceedingly small change in this case. I'm also seeing about 0.2 ppm/% change on Vdd1, by the way.

[iMo]

I would not underestimate voltage drops on the trace's resistances. When chasing uVolts even several centimeters of a 0.25mm wide trace (for example) play a role. The traces you are using are 35um thick. Hopefully HP is not using thicker copper there..

PS: below my traces model (it has got TC as well).
"m" means millimeters, 35um copper by default.

[Zondar]

IMo: True, but traces on an IC like U180 are a lot thinner and narrower and higher resistance per square (albeit shorter) than on these boards. Apples and oranges, but still interesting to compare.

Your diagram assumes that all power is going through long thin traces. That's not the case. Power is delivered via planes with <=1 mOhm resistance each. Switch on-resistance is considerably higher (like orders of magnitude) than the worst associated trace resistance, too. Also, ADC currents flow through kOhm resistors, making any associated trace resistance (a small fraction of an Ohm) almost meaningless. I was more worried about other signal integrity issues such as cross-talk, return paths, etc. Paying extra for thicker copper would be understandable, though.

But that reminds me of something Kleinstein said long ago: that some or all of the resistor values should be adjusted to include the on-resistance of the switches. So if the switches have 2.4 Ohms on-resistance, perhaps an 80k resistor should really be 79,997.6 Ohms, etc. If you knew the trace resistance, you could throw that in too, but it would be almost negligible.

[iMo]

That is true, but you have much more circuitry and traces there. So the chip and pcb is not 1:1.
And while switching with the stuff the currents get even higher (higher parasitic capacitances on your pcb.

[DB4UCH]

It's not clear to me that a constant, uniform, delay of ~4 ns, i.e. if the rising and falling edges are both delayed by the same amount, should have a negative impact. This just shifts everything uniformly to the right by ~4 ns. As long as that's much lower than the clock period to avoid collisions with other actions, it should make little difference.
What could be important is any differing latency of rising vs. falling edges. Quite often falling edges are faster than rising ones due to the difference in mobility between electrons and holes. Sometimes efforts are made to equalize these (e.g. the P-channel pull-ups are made larger to compensate), but often not. A difference in rise/fall times effectively leads to a difference in latency, even if there is no explicit extra delay.

As long as the offset is short enough it shouldn't be causing issues, the thing is, if you don't use the inverter the control signals for the switches on the NU180 can reach slightly into the next clock cycle (still working at that point but not great). That’s why I tried to match it.

As for difference in delay between rise and fall times: I get ~ 2.4ns by which the falling edge is faster than the rising one (after the FF). As for the signals I use SLA and S7 after the FF.

About power consumption: You were presumably powering Vdd1 externally while the board was still loaded onto A3, but with that pin disconnected from A3? If it's disconnected, then Vdd2 will remain powered through the A3 board and will be unrelated to the voltage you apply to Vdd1. I'd suggest trying to change Vdd2 independently too, which is simple as it does not need to be disconnected from the A3 board (the diode will cut off and leave it floating if it's raised up a little, but I wouldn't lower it much).

I cut off the pin from the NU180, so no connection from the NU180 to VCC to the A3 board exists anymore. I don’t remember the state the switch supply was in for my first measurement, so I redid the variation of the supply voltage with the jumper set to VDD1 and got the same susceptibility to supply change.

Greetings,
Simon

[Zondar]

You say you redid it with the switch supply set to Vdd1? Yes, I'd expect to see the same. Did you try changing only Vdd2 to the switches? GND2 will also change the digitized value somewhat.

One question is whether the voltage sensitivity is "normal" in the sense that a genuine U180 will show the same tendency. I suspect this is the case.

The digital 5V on A3 ("Vdd1") does not appear particularly well controlled. My machine reads that as 4.887 V, for example.

About asymmetric delays: The 2.4 ns you measured is within reason, but a little worse than I was expecting. Potentially more serious is something I've worried about and discussed a time or two in the past: The switches themselves react differently to rising and falling edges on its control signals. The quoted T_on=19 ns (rising control edge to output) and T_off=7 (falling control edge to output) are certainly not equal, and well exceed the 2.4 ns you measured. If the numbers are accurate, then combining them results in a 19-2.4-7ns difference of almost 10 ns. If that's real, then it seems enough to cause a problem.

Looking at the time that the slope changes, as you did, is probably the best way to measure this in-situ. If the up and down slopes are supposed to have equal durations (apparently not in the posted case), can you see how close to true that is?

(P.S., using "Vss" is kind of ambiguous. Maybe stick with Vdd1, Vdd2, GND1, GND2, etc., as that's what's used on the schematics.)

[DB4UCH]

About asymmetric delays: The 2.4 ns you measured is within reason, but a little worse than I was expecting. Potentially more serious is something I've worried about and discussed a time or two in the past: The switches themselves react differently to rising and falling edges on its control signals. The quoted T_on=19 ns (rising control edge to output) and T_off=7 (falling control edge to output) are certainly not equal, and well exceed the 2.4 ns you measured. If the numbers are accurate, then combining them results in a 19-2.4-7ns difference of almost 10 ns. If that's real, then it seems enough to cause a problem.

I get about 4 ns for which the switches on the NU180 are faster for the falling vs the rising edge, although I measured the control signal vs ringing at the appropriate 80k resistor, so not very precise. I don't really see a way to compare the opening and closing behavior between the NU180 and the U180 as I don't have access to the switches in the U180 and the ramp itself depends on more factors. My previous measurement was kind of comparing them as a black box.

Did you try changing only Vdd2 to the switches? GND2 will also change the digitized value somewhat.

Not yet, I think I will do this tomorrow, although I think that it shouldn't influence the gain by much if by anything at all.

Greetings,
Simon

[Kleinstein]

The original U180 should also react somewhat to changes in the supply, especially for VDD2. They use the gate voltage modulation to correct for INL (U² part from nonlinear R_on).  This is kind of based on having a slightly different supply to the input path switch. To a large part (e.g. the thermal effect for the diodes) this would only be a slow change in the overall gain and gain TC.

The asymmetry in the switching times for on and off should not be that bad. It is effectively a breake before make time. The MS-adc is made that there is a constant number of switching events and a fixed delay in the time would give a fixed charge and thus a fixed offset. The AZ mode (and AZ once as start to non AZ) will take care of an offset. For the reference switching via current steering it is anyway of off time that matters: when an input path is switched off it is obviously the off part that matters. When a path is turned on, the link to ground is separated first and during the breake before make time the current charges the parasitic capacitance at the switch common node. The charge from there than still flows to the integrator, when the other switch half turns on.
With a reference current of 12V/80 K = 150 µA and some 10 pF and 10 ns this would reach some 150 mV, still below the level the parasitic diodes activate. AFAIR the capacitance of the AD734 switches is more like 30 pF and thus less voltage, though still the same 1.5 pC of charge.

The high ref. current paths with 20 K resistors could be a slight issue, but I would consider the fast part less critical.

[DB4UCH]

Did you try changing only Vdd2 to the switches? GND2 will also change the digitized value somewhat.

Not yet, I think I will do this tomorrow, although I think that it shouldn't influence the gain by much if by anything at all.

Just changing vdd2 seems to lead to a change in gain of about 0.17PPM / % of supply change.

[Zondar]

Thanks Simon.

The remaining issues are so small that it's no surprise that they are difficult to pin down.

We may need to hold Vdd2 constant while varying Vdd1 as well, to separate out the two. But Vdd2 is much more likely to bear responsibility. If it's the main culprit, I think regulation could help, and that's pretty easy to do.

To the extent that a 50% duty cycle is not maintained (due to rise/fall delays, etc.), the switch-closed durations will differ. It sounds like we have at least 2.4 ns, possibly up to 10 ns or so. This should only matter when both sides of one SPDT switch are used, e.g. alternately, to execute a function.

(I thought of a very bad solution to the timing variation issue: put two of the switches in parallel, with the analog inputs crossed.) 

[Kleinstein]

Except for the dummy resistor for the gate voltage modulation the SPDT switches all use both parts and are used for current steering. So the resistor for the input current a the common pin. One switch is to ground and the other to the integrator input. As explained before, the dead time should not matter and the relevant timing is for the switch off part.

The main reference currents are already split in 2 haves and kind of used as 2 switches in parallel, though with separate resistors to ensure current sharing.

[Zondar]

As mentioned above, my worry is not about switch open times, but about the uniformity of switch closed times. I might dig out my ADG test board and investigate a little. But if you think ~10ns difference would not matter, then maybe there's no need to be concerned.

If we feel that the sensitivity to Vdd2 is serious enough that it needs to be addressed, then generating a local Vdd2 can help. Something like the TI LP5907, 4.5V output, taken from Vdd1 should do.

Unfortunately, I can't find any regulator that outputs below -1V, and I did note sensitivity to variation of GND2 as well. One option is to abandon the pure plug-in stance and include a flying lead, probably to -18V (using -12V is probably a bad idea), and regulate to +2.5 and -2.5 (or maybe 3.3V and -1.25 or so, depending on compatibility with the digital signals). If it's found that Vdd1 is also an issue, then we can regulate that too, e.g. from +18V.

Opinions?

[Kleinstein]

It is not at all clear if a negative voltage is needed at all and if it is worth the trouble. The negative voltage may help a little with the charge injection (it gets better if the supply would be shifted to the negative side. Another issue is that the charge injection in the datasheets are for the turn off case only. With the NU180 the relevant situation is a combined turn on and turn off of 2 switches.

However we then somehow run into issues with the control signals and supply voltage that get too large and not low enough.

A low positive supply for the switches would also need a lower supply for the CPLD and FF.

[Zondar]

I understand the point about the negative voltage. I looked at those signals and indeed they barely budge from zero. However, given that HP included a negative supply, which I agree with for what that's worth, I feel it should be included until proven that it's not needed. Also, I'd expect the switches to perform a little worse if we really are right up against a rail.

Anyway, I updated my V0.5 design to include regulation for the positive side, e.g. 2.5-4.5V, with the option to use Vdd2 as-is. The CPLD would be fine, as the SN54LVC574 flip-flop, for example, allows operation down to 2.5V (2.2V, actually) with 5V tolerant inputs.

I'm still thinking about the negative side, but one option is to allow switching from GND2 and a negative regulator, maybe the ADP7182, with a flying lead to -18V. It would be easy to hack that to try 0V only (I'd have to cut a pin to try it now).

Using +/-2.5V could provide a tiny improvement in linearity and on-resistance over the current +4.4, -0.6V.