Multislope Design

[Rerouter]

Still playing with math, adding up error sources, and testing assumptions of various parts, Here is where it is currently, essentially only power supply left, These are KiCad design files, and your free to do with them as you please, right now no pins have been swapped so it will still support Klein's original software.

Learning all the fun little effects is taking me some time, as not all of them are the easiest thing to wrap my head around. and want to check that before I pack it up tightly.

[SilverSolder]

This has to be one of the most ambitious hobby electronics projects ever?

Any chance of some straight PCB art work in a pdf, or some Gerber+drill files?

[Kleinstein]

In the other thread about my ADC version, there should be some PCB pictures. As a first test there are a few changes needed (though not too many to be done with bodges - so usable for me), so I would no recommend a straight 1:1 copy. Also the combination of THT and SMD parts is a little unusual (but it helps with routing and bodges).

Just building a multi slope ADC around an µC or FPGA (whatever one is more comfortable with) is not that ambitious - it just has the combination of critical analog and a little slightly advanced programming.

The tricky part comes if one wants to aim for really high performance. Some of the thoughts in the layout are likely overkill, but it helps of one can exclude some known possible error sources. At the sub ppm level, there are enough small effects we likely have overlooked so far.

[SilverSolder]

[...] The tricky part comes if one wants to aim for really high performance.  [...]

Eight digits or bust!     

[iMo]

As I saw the topic on the new Microchip's atmega4809 (28-40pin PDIP, 6kB ram, 48kB flash) the first thing which came to my mind was Kleinstein will certainly go for it with his next MS ADC revision:

..
- Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with up to four programmable Look-up Tables (LUT)
– One Analog Comparator (AC) with a scalable reference input
– One 10-bit 150 ksps Analog-to-Digital Converter (ADC)
– Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3
..

[jaromir]

Respawning this old thread to share news in a development which are not worthy new topic yet, but fits this topic.

Since the original ADC I showed before in [1] and subsequently [2] and [3] is too old for me, I played with DIY ADC some more and put together different ADC implementation with residual integrator reading, kind of similar to HP34401 ADC. The integrator is never reset to any state, just continues integration where it left off before in previous reading.
This ADC is going to be a part of another project to be released soon (including full schematics and source codes, of course), so as a teaser I'm attaching a photo of my prototype (there is a few unneeded parts to be removed for final version) and quick INL test against Solartron 7081. Above 4V the linearity is quite repeatable (under 0,1ppm), below that it's getting significantly worse to around 0,3ppm - this is probably caused by variable voltage on integration capacitor, as a function of input voltage. I'll investigate this some more and try to fix it.

[1] https://www.eevblog.com/forum/projects/multislope-design/msg2378133/#msg2378133
[2] https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/
[3] https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/

[ali_asadzadeh]

jaromir I'm waiting  to be surprised

[jaromir]

The project I'm working on - and containing this ADC - progressed some more and I went from ADC prototype to final board. While doing this I made some minor touches to the ADC schematics and reworked the PCB layout. The 0,3ppm Himalaya below 4V went away, now I feel like I'm limited by noise of the setup - both ADC and Solartron 7081 I'm comparing against. Attached is typical INL result - just quick scan taking few minutes, to get more precise result I'd need to do multiple longer scans and average results. For now I'm OK-ish with this.
Attached is also photo of the work in progress project - ADC is the middle board. More updates will follow.

[iMo]

I came across the LD111A chip - the analog front end - (I found one in my junkbox, date code 83') and I started to read the DS (attached).
Is that a kind of the multislope adc? It does not seem to me a dual slope one - at the first glance..
I shortly was thinking an mcu attached could go to 5digits, perhaps..  

[Kleinstein]

The LD111A is only the analog part of the converter. Together with the LD110 logic part the converter is a kind of low end multi-slope converter. However only with a multi-slope run-up and than with a simple and fast 1 speed rundown. With a difference control logic the analog part could likely also run in a dual slope mode.

The part with the AZ capacitor is unusual and can limit the maximum integration time. I am a bit confused that they suggest an integration capacitor scaling with the integration time - this is normally not needed for a MS ADC, but more like a point with a dual slope ADC.

Especially with the relatively low clock suggested for the LD110 the resolution is a bit limited. With the suggest relative high 8.2 V reference (should also work with 7 V) chances are the noise level is OK for higher resolution. There are still a few uncertainties about the amplifier's noise (especially 1/f noise part). It is also not clear how fast / accurate the comparator is.

The switching is before buffer amplifiers and thus possibly quite some settling time needed. So the speed of the run-up part could is limited.

AT first glance the ADC looks like it could be low noise and good linearity. Not so sure about the actual performance - they had an older version (non A) with seemingly some problems with linearity.
The quality of the input buffer could limit the linearity.
0.1 LSB of peak to peak noise suggests that with more timing resolution a higher overall resolution could be possibly, though not sure about 5.5 digits (still possible).
Reasonable performance even with a 20 mV Fs range suggests that the chip can be low noise, especially with a high FS range.
As a positive thing it looks like it did read the input for a relative large fraction of the time ( ~ 2/3), compared to the classic 7106 that only reads the input for 1/4 of the time.

I still would not use the old hard to get chip, but prefer seprate swiches and OP-amps. After all the LD111A is only the analog part with a few CMOS switches and OP-amps. It does not take that much analog parts to create a multi-slope ADC with µC control. Many µCs already include a comparator. With a µC and low offset OP-amps one can usually get way without an analog auto zero phase and do digital auto zero, like the AZ mode in higher end DMMs.

[iMo]

@Kleinstein: thanks, yeah, not suggesting the chip for new designs, nope.. Btw., in meantime I've double checked an old dmm here and I've found the chip - the 111 without "A" version - in one of my old dmms I still use as an ammeter only (the M-3001 made in Hungary, around 1980) and my 111A is a direct replacement, so it is a spare one
My first idea has been to play with the 111A analog part while bit banging the 2 control signals out of an fpga or mcu with a "better algorithm", thus getting a better resolution. The 111A allows 10uV resolution with 20.00mV setting DS says, so the chances really are it could work with more digits.. 

[Kleinstein]

The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.

[iMo]

The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.

Here you are - the LD120/121A combo with 4.5 digits (DS attached). The analog chip is identical with the LD111A (my bet the silicon is the same) and the digital chip does 4.5digits with more clocks per charge bucket. Also the DS reads better in the operation section. They wired the AZ cap (in series with a resistor) against GND there (I saw it with 111A as well). Pretty popular ADC chipset around 1980, indeed.
I still do not understand fully how they do the fast rundown, on the other hand you could do the measurement of the residual int cap charge with an ADC in the mcu, as Jaromir does above.. 

[Kleinstein]

The rundown is done essentially the same as the run-up, just with a 0 V input signal and stopping at zero crossing. Ideally there would be an extra phase to make sure that the final stop is always from the same direction. Not sure if the is implemented in the LD120.
By nature this rundown is very fast, like 2 runup-steps at most (e.g. 100 µs range)  and thus only some 16 counts max. With external timing one could get higher resolution of this time - the LD120 uses a rather low clock (e.g. 168 kHz) by todays standards for a µC.
Not having a stop option makes it a bit tricky to use an auxiliary ADC for the residual charge.

[iMo]

PS: I've been digging more and more into it - here is the Siliconix 1982 Analog Switch and IC Product Data Book with a lot of detailed info on it (from the page 263 up), incl. app notes and those DS above, ie. there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..
Btw 260 pages with zillion of analog switches, in 1982

[David Hess]

there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..

I became very familiar with the Siliconix LD series because Tektronix used them in their bench multimeters in the 1970s.  The external buffer version was introduced to correct a defect in the original design; the integrated CMOS buffer has typical terrible CMOS common mode rejection which severely limits linearity of the converter.  An external JFET precision operational amplifier corrects this somewhat.

Intersil avoided this problem entirely by performing the automatic zero cycle with the input to the buffer set to the input signal level, so the automatic zero corrects the offset at the common mode input voltage.