Multislope Design

[Rerouter]

Still playing with math, adding up error sources, and testing assumptions of various parts, Here is where it is currently, essentially only power supply left, These are KiCad design files, and your free to do with them as you please, right now no pins have been swapped so it will still support Klein's original software.

Learning all the fun little effects is taking me some time, as not all of them are the easiest thing to wrap my head around. and want to check that before I pack it up tightly.

[SilverSolder]

This has to be one of the most ambitious hobby electronics projects ever?

Any chance of some straight PCB art work in a pdf, or some Gerber+drill files?

[Kleinstein]

In the other thread about my ADC version, there should be some PCB pictures. As a first test there are a few changes needed (though not too many to be done with bodges - so usable for me), so I would no recommend a straight 1:1 copy. Also the combination of THT and SMD parts is a little unusual (but it helps with routing and bodges).

Just building a multi slope ADC around an µC or FPGA (whatever one is more comfortable with) is not that ambitious - it just has the combination of critical analog and a little slightly advanced programming.

The tricky part comes if one wants to aim for really high performance. Some of the thoughts in the layout are likely overkill, but it helps of one can exclude some known possible error sources. At the sub ppm level, there are enough small effects we likely have overlooked so far.

[SilverSolder]

[...] The tricky part comes if one wants to aim for really high performance.  [...]

Eight digits or bust!     

[iMo]

As I saw the topic on the new Microchip's atmega4809 (28-40pin PDIP, 6kB ram, 48kB flash) the first thing which came to my mind was Kleinstein will certainly go for it with his next MS ADC revision:

..
- Event System for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with up to four programmable Look-up Tables (LUT)
– One Analog Comparator (AC) with a scalable reference input
– One 10-bit 150 ksps Analog-to-Digital Converter (ADC)
– Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3
..

[jaromir]

Respawning this old thread to share news in a development which are not worthy new topic yet, but fits this topic.

Since the original ADC I showed before in [1] and subsequently [2] and [3] is too old for me, I played with DIY ADC some more and put together different ADC implementation with residual integrator reading, kind of similar to HP34401 ADC. The integrator is never reset to any state, just continues integration where it left off before in previous reading.
This ADC is going to be a part of another project to be released soon (including full schematics and source codes, of course), so as a teaser I'm attaching a photo of my prototype (there is a few unneeded parts to be removed for final version) and quick INL test against Solartron 7081. Above 4V the linearity is quite repeatable (under 0,1ppm), below that it's getting significantly worse to around 0,3ppm - this is probably caused by variable voltage on integration capacitor, as a function of input voltage. I'll investigate this some more and try to fix it.

[1] https://www.eevblog.com/forum/projects/multislope-design/msg2378133/#msg2378133
[2] https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/
[3] https://www.eevblog.com/forum/metrology/diy-6-digit-handheld-volohmmeter/

[ali_asadzadeh]

jaromir I'm waiting  to be surprised

[jaromir]

The project I'm working on - and containing this ADC - progressed some more and I went from ADC prototype to final board. While doing this I made some minor touches to the ADC schematics and reworked the PCB layout. The 0,3ppm Himalaya below 4V went away, now I feel like I'm limited by noise of the setup - both ADC and Solartron 7081 I'm comparing against. Attached is typical INL result - just quick scan taking few minutes, to get more precise result I'd need to do multiple longer scans and average results. For now I'm OK-ish with this.
Attached is also photo of the work in progress project - ADC is the middle board. More updates will follow.

[iMo]

I came across the LD111A chip - the analog front end - (I found one in my junkbox, date code 83') and I started to read the DS (attached).
Is that a kind of the multislope adc? It does not seem to me a dual slope one - at the first glance..
I shortly was thinking an mcu attached could go to 5digits, perhaps..  

[Kleinstein]

The LD111A is only the analog part of the converter. Together with the LD110 logic part the converter is a kind of low end multi-slope converter. However only with a multi-slope run-up and than with a simple and fast 1 speed rundown. With a difference control logic the analog part could likely also run in a dual slope mode.

The part with the AZ capacitor is unusual and can limit the maximum integration time. I am a bit confused that they suggest an integration capacitor scaling with the integration time - this is normally not needed for a MS ADC, but more like a point with a dual slope ADC.

Especially with the relatively low clock suggested for the LD110 the resolution is a bit limited. With the suggest relative high 8.2 V reference (should also work with 7 V) chances are the noise level is OK for higher resolution. There are still a few uncertainties about the amplifier's noise (especially 1/f noise part). It is also not clear how fast / accurate the comparator is.

The switching is before buffer amplifiers and thus possibly quite some settling time needed. So the speed of the run-up part could is limited.

AT first glance the ADC looks like it could be low noise and good linearity. Not so sure about the actual performance - they had an older version (non A) with seemingly some problems with linearity.
The quality of the input buffer could limit the linearity.
0.1 LSB of peak to peak noise suggests that with more timing resolution a higher overall resolution could be possibly, though not sure about 5.5 digits (still possible).
Reasonable performance even with a 20 mV Fs range suggests that the chip can be low noise, especially with a high FS range.
As a positive thing it looks like it did read the input for a relative large fraction of the time ( ~ 2/3), compared to the classic 7106 that only reads the input for 1/4 of the time.

I still would not use the old hard to get chip, but prefer seprate swiches and OP-amps. After all the LD111A is only the analog part with a few CMOS switches and OP-amps. It does not take that much analog parts to create a multi-slope ADC with µC control. Many µCs already include a comparator. With a µC and low offset OP-amps one can usually get way without an analog auto zero phase and do digital auto zero, like the AZ mode in higher end DMMs.

[iMo]

@Kleinstein: thanks, yeah, not suggesting the chip for new designs, nope.. Btw., in meantime I've double checked an old dmm here and I've found the chip - the 111 without "A" version - in one of my old dmms I still use as an ammeter only (the M-3001 made in Hungary, around 1980) and my 111A is a direct replacement, so it is a spare one
My first idea has been to play with the 111A analog part while bit banging the 2 control signals out of an fpga or mcu with a "better algorithm", thus getting a better resolution. The 111A allows 10uV resolution with 20.00mV setting DS says, so the chances really are it could work with more digits.. 

[Kleinstein]

The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.

[iMo]

The analog side should be OK for higher resolution. So in theory an upgrade to the LD110 for a 4.5 digit or similar version would likely have been viable. Not really attractive today with cheap ADC chips for the low end 5 digit range.

Here you are - the LD120/121A combo with 4.5 digits (DS attached). The analog chip is identical with the LD111A (my bet the silicon is the same) and the digital chip does 4.5digits with more clocks per charge bucket. Also the DS reads better in the operation section. They wired the AZ cap (in series with a resistor) against GND there (I saw it with 111A as well). Pretty popular ADC chipset around 1980, indeed.
I still do not understand fully how they do the fast rundown, on the other hand you could do the measurement of the residual int cap charge with an ADC in the mcu, as Jaromir does above.. 

[Kleinstein]

The rundown is done essentially the same as the run-up, just with a 0 V input signal and stopping at zero crossing. Ideally there would be an extra phase to make sure that the final stop is always from the same direction. Not sure if the is implemented in the LD120.
By nature this rundown is very fast, like 2 runup-steps at most (e.g. 100 µs range)  and thus only some 16 counts max. With external timing one could get higher resolution of this time - the LD120 uses a rather low clock (e.g. 168 kHz) by todays standards for a µC.
Not having a stop option makes it a bit tricky to use an auxiliary ADC for the residual charge.

[iMo]

PS: I've been digging more and more into it - here is the Siliconix 1982 Analog Switch and IC Product Data Book with a lot of detailed info on it (from the page 263 up), incl. app notes and those DS above, ie. there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..
Btw 260 pages with zillion of analog switches, in 1982

[David Hess]

there is the LD122 with an external input buffer for low noise app and the DS there claims 1uV resolution with 20mV range, they use OP07 as the input buffer and LM399 for a 4.5digit meter..

I became very familiar with the Siliconix LD series because Tektronix used them in their bench multimeters in the 1970s.  The external buffer version was introduced to correct a defect in the original design; the integrated CMOS buffer has typical terrible CMOS common mode rejection which severely limits linearity of the converter.  An external JFET precision operational amplifier corrects this somewhat.

Intersil avoided this problem entirely by performing the automatic zero cycle with the input to the buffer set to the input signal level, so the automatic zero corrects the offset at the common mode input voltage.

[MiDi]

True8DIGIT - Towards a true 8‐digit digitiser: https://true8digit.eu/
The Project flyer gives an overview of the project.
Project Progress Presentation at EURAMET TC-EM SCs Joint Meetings at IPQ
Publications: https://zenodo.org/communities/22rpt02

[MiDi]

Has someone done noise calculations and could share formulas?
There is a lot of general information about noise here and in other threads about MS / integrating ADCs, but mostly only the results.
Would save me a lot of time, as this is not trivial, especially noises related to switching.

Want to get a rough estimation for 3458A ADC noise limits and other projects would benefit too.
3458A noise: https://www.eevblog.com/forum/metrology/3458a-worklog/msg5873640/#msg5873640

[Kleinstein]

I have done noise calculations for MS ADCs.  It is not so much one formular, but a list of contributions to the noise.

A main point to get the noise is to look at it similar to the error propergation formular. So take the parts that contribute to the result and also include terms that are ideally zero. This gives 2 groups of noise:
1) charge going tothe integrator. This is more or less directly comparable to the input signal and thus usually  has the BW from there (SINC function and 1/(2T) bandwidth).
2) noise in the measurement of the final and start charge. That is mainly the final comparator step with usually the slope amplifier that sets the bandwidth. In principle the reset also contributes but in the 3458 like design this has a lower bandwidth (needs to, for stability).

For switching it is mainly jitter. As the RMS timing error times the reference strength (for the 3458: 1.25 * 12 V) and square root of the number of switching events. The clock part is correlated and the switch parts are not correlated. However one is anyway missing good data to start with.

Another switching related noise part is from the capacitance that is disconnected or connected to the integrator input. This is the switch capacitance towareds the ref. resistors. These contribute with KTC type reset noise and again the square root of the number of switching events.

I have a crude spread sheet for the noise calculation, that is attached. It may be a bit hard to read though.

[MiDi]

Thanks for the gold Kleinstein.
The noise/jitter from the comparator is not included, is it negligible?

Playing with the numbers it matches the results for the 3458A mods for flat noise quite good - have to compare it in more detail.
In general it shows that there is not much more improvement possible for flat noise part, as the main contributors are the integrator input resistors and jitter.
As you already mentioned, there might be bit of improvement from filtering the reference - from the calculation there should be insignificant difference between short and FS, measurements differ quite a bit.
Have to dig deeper into the high 1/f noise and if it agrees with calculation - there might be some room for improvement left.

[Kleinstein]

With a gain of 10 or more from the slope amplifer the noise from the comparator should be a rather small contribution. In addition there are essentially no data for noise with comparators.
With 1 and 10 PLC convesions the noise part from the final charge is anyway not that relevant, especially with a rather small integrator capacitor like in the 3458. In variants with a rather large capacitor (e.g. Keithley 2001 with 10 nF and 58 K at the input) the final charge part could be more relevant.

The noise calculation is for the zero input, but for the ADC noise alone there should not be that much difference. There can also be a little more noise from the reference amplification (7 V to +-12 V in the 3458), but this should not be that much.  An added part is low frequency reference (both references) noise if a different external reference is used.

One gets 1/f noise from the OP-amp at the integrator and a little less (lower noise gain and lower resistance for current noise) from the reference inverter. Not so good resistors can also contribute 1/f noise. I had that with NOMCA (TaN) type resistors and also some THT resistors. In my design they contributed more 1/f noise than the OP-amps (OPA141 and OPA202). One would see 1/f noise in the ratio of 1 PLC and 10 PLC noise.

[MiDi]

The noise calculation is for the zero input, but for the ADC noise alone there should not be that much difference. There can also be a little more noise from the reference amplification (7 V to +-12 V in the 3458), but this should not be that much.  An added part is low frequency reference (both references) noise if a different external reference is used.

Good note, thought it was for FS.
So then for an input short there is negligible improvement for filtering the reference for current 3458A mods (ADR1000 with Iz=10mA has ~10nV flat noise).
Note: for input short the LF noise of the reference cancels out as +-refs contribution are balanced, for other inputs the ref noise scales with unbalanced +-refs.

So for FS input at least need to add the noise gain scaled reference noise, anything else?

[Kleinstein]

There is still a use of fitlering the reference a little with a shorted input. It is for the higher frequencey reference noise. The capacitors at the reference amplification give partial filtering, but the +12 V ref of the 3458 would still see much of the higher frequency ref. noise.
This higher frequency ref. noise actually gets less important at full scale. However usually the LF noise of the reference is higher and there filtering is tricky and not as effective.

For the ref. noise there are 3 frequency bands that can have an effect:
1) very low frequencies like < 1 Hz directly acting as noise to the ADC scale. Here filtering is very limited.
2) noise at around the speed of the AZ loop (2.5 Hz for 10 PLC , 25 Hz for 1 PLC). This part has an effect because the zero reading in the AZ loop is hardly looking at the reference. This gives some "aliasing" around this frequency. Here filtering can work, especially for the 1 PLC case.
3) frequency components around the feedback modulation (e.g. some 160 kHz for the 3458, but also some subharmoics in the FB patterns). This part is easy to filter. It is not so clear how much noise the LTZ1000 ref. has in this band.
The exact frequencies change with the input voltage, but the overall BW should be 1/(2Tint) like the input. With a higher voltage some of the BW goes to the LF part.

p.s.
If the resistors show 1/f noise than this can get higher with a full scale voltage than with a short, as there is less averaging over multiple resistors.

[MiDi]

True8DIGIT - Towards a true 8‐digit digitiser: https://true8digit.eu/
The Project flyer gives an overview of the project.
Project Progress Presentation at EURAMET TC-EM SCs Joint Meetings at IPQ
Publications: https://zenodo.org/communities/22rpt02

New exciting publication: Composite Operational Amplifiers for front-end and integrator

[wanghar]

New exciting publication: Composite Operational Amplifiers for front-end and integrator

Thanks MiDi for sharing the link! After reading this document, I now understand the why behind using Q110 (JFET) in the 3458A's integration circuit.