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« Last post by BrianHG on Today at 08:22:28 pm »
Try shrinking the clk_0 phase by 2-5 ns. The internal clock will be 8mhz either way. Going to 10mhz might only affect the automatic 'PLL Bandwidth', changing it from 'low' to 'medium' as 5mhz and 10mhz may be a transition point for the pll's phase comparator and lying to quartus just makes quartus jump up that setting by 1 making the PLL more responsive to a noisy clock source. You haven't actually changed the PLL's output clock frequency. EG: make a spare IO pin equal to the PLL clock and check the 2 signals together on your scope, clkin and clkout, you will see they are the same. (IE, if your source clock has some noise, then the PLL output needs to track that noise for your circuit to run good.)
In your design, you do not have any properly clocked ram. All you have are 3 static rams. The way they are written makes some things flaky as you have some posedge and negedge clocks as well surrounding their address controls, however, when copying someone else's hardwired logic or IC process, this may be the quickest route to success.
Using a clk_1 output running at 90 deg out of phase from clk_0 to latch/clock the ram data or address controls can help. Or making clk_1 run at 4x where you clock the ram's address and controls running at this speed would also help.
Again, this design uses so many different clocks at so many little points that it would be hell to fiddle with it. If you are re-writing your own code, then you might want to take things your own way.
The design appears to clock it's ram from 'different' multiple input source conditions, including the main clock. Delaying the main clock with the phase probably allows all the the states of the multiple inputs to settle before any action takes place. With multiple negedge and posedge triggers in the code, you would need to decide which things gets moved where.
When setting up the PLL did you try -45 deg, or 180+/-45deg to see if you get a larger sweet spot of operation?
Memory is simple in verilog. However, the way data is being written with multiple write clock sources for 1 ram instead of what we are used to seeing, 1 clock source for the ram's write port, then multiple selectable states for the 'write-enable'. Same for the read port. It could be the same system ram clock, or, it's own clock, preferably with a latched read address, then latched data output for best FMAX performance. Again, this design uses the ram in static read mode, though, at 8mhz, the max10 can do this with ease as having the read address and data latched would allow the max10 to run the ram at a whopping 250mhz. But when you send a read address, that address data output is pipe delayed by 2 clocks.
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