Recent Posts

1

FPGA / Re: Help on translate schematics to Verilog.

« Last post by BrianHG on Today at 03:35:46 pm »

Your 'buffered' clock seems worse than original. And 74LS series is a VERY SLOW. It should not be used as clock buffer (and used at all on 8MHz, IMHO).

> When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.

Very likely that there is some problem with RTL.

We do not know what his logic is doing.
If he is using the FPGA to drive data on a bus and it is replacing TTL logic, it could be a setup & hold issue where the FPGA responds so fast that the relevant data is removed too quick, or incoming clock data being latched too soon.

Remember, we are dealing with a beginner trying to replicate drawn 74LS ttl schematics.

I would say add 1 to 3 'LCELL' buffers for the clock input on the FPGA to replicate the external buffer delay.  Again, this is the wrong way to do things, but if it works, it illustrates a timing issue, not a noisy or weak signal issue.

Redoing the OPs code from a WYSIWYG code style to what the logic supposed to function like or inverting the clock at the right points in his code would probably help.  The other choice is to enable Quartus' WYSIWYG feature in their compiler setting window to ensure Quartus isn't optimizing out his code to a simpler faster design.

2

Projects, Designs, and Technical Stuff / Re: Thoughts on How to Raise SMD LEDs Above the Board

« Last post by Bucataru on Today at 03:35:16 pm »

I have a similar issue. How do I raise this UV sensor (GUVB-S11SD) by 3mm or even higher? Light pipes, either glass or plastic, aren't transparent to these wavelengths of light.
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3

Test Equipment / Re: New Rigol 16-bit function generators DG800/900 series

« Last post by Njk on Today at 03:32:35 pm »

Yes it does because the limiter is still an "experimental feature". Set up a petition at change.org

4

Test Equipment / Re: Test Equipment Anonymous (TEA) group therapy thread

« Last post by Zucca on Today at 03:30:08 pm »

In case you missed it...

https://www.eevblog.com/forum/buysellwanted/fs-(us-to-xx)-tek-afg3252-like-new-single-owner-$3k/

It will be hard to sell, to expect the price to go down...

5

Networking & Wireless / Re: Network attached usb hub

« Last post by dietert1 on Today at 03:28:57 pm »

At ebay, when searching for "NAS kit", i found "SunFounder NAS Kit für Raspberry Pi" for € 33.

Regards, Dieter

6

Test Equipment / Re: Siglent Bench DMMs SDM3065X, SDM3055 and SDM3045X

« Last post by Kleinstein on Today at 03:26:58 pm »

The resolution looks rather limited. At what speed is the DMM running. The scaling is also not telling much just as the KS original. So it is a bit hard to judge on the noise and step size.

For the 4 lm399 refs I have measured and the reports found so far the popcorn noise jumps are pretty consistant. Much larger jumps could as well be from other parts then just the reference.
As a test one could have a longer time series with a stable resistor (e.g. 20 K) and see if there are comparable jumps somehow. This would test slightly different parts of the meter, eliminating the reference.

7

Computers / Re: Format a 256GB pendrive with FAT32 using a windows 10 pc

« Last post by Mechatrommer on Today at 03:22:30 pm »

M$ beancounters saw that 40GB disks are right behind the horizon and thought it would be cool if those disks used NTF$.
They came up with some crazy pseudotechnical justification for crippling FAT32 and sold it to a random autistic developer.

plummer in the video denied that. then who's the autistic developer?

8

RF, Microwave, Ham Radio / Re: Using spectrum analyzer to debug NRF24 module

« Last post by sairfan1 on Today at 03:20:12 pm »

Thaks, that post looks very interesting.  Let me work on it and I'll get back.

9

Metrology / Re: Why don't we see more TDC based high-resolution ADCs?

« Last post by Kleinstein on Today at 03:19:06 pm »

To spitball a TDC based DMM front end:

Exactly the same as a regular integrator but uses high speed comparators to trigger at, say, 0V and Vref/2 and then measure the time to integrate. You could easily linearize this and calibration could be done automatically I'd assume. PVT probably kills you but for a fixed temp, voltage and process -- n=1 -- I suppose you could do quite well.

That would be a kind of single slope converter. So 2 steps back from a multi-slope. The problems start with a integration time that is not fixed but depends on the signal - so no easy mains suppression.

10

Test Equipment / Re: SDS800X HD Actual Use Cases

« Last post by mawyatt on Today at 03:18:54 pm »

Here's a few uses with the Bode plot showing filters.

These are interesting RC filters that exhibit a "greater than unity gain" yet have no inductors, nor transformers, transmission lines, switches, non-linear elements, or active devices, just a couple resistors and a couple capacitors.

One is a Low Pass and the other a High Pass, and both show ~0.66dBV gain. Probably not much use but interesting anyway, analysis left up to the reader

Included some LTspice Sims for reference.

BTW a single JFET also exhibits a Passive Voltage Gain without any additional components, nor power supply!!

Gotta love this little SDS800, puts a grin on our face every time we use it

Will add more later if folks are interested.

Best