Recent Posts

1

Microcontrollers / Re: How to create custom bootloader in esp8266

« Last post by digitalectron on Today at 08:22:53 am »

Thank you for taking the time to answer my question. I was wondering if there would be any problems booting the program if the power goes out while updating the ESP8266 firmware?

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Projects, Designs, and Technical Stuff / Re: Accurate sine wave in terms of amplitude

« Last post by moffy on Today at 08:17:36 am »

In the application note: https://www.analog.com/media/en/technical-documentation/application-notes/an43f.pdf
from page 30 onwards a number of precision Wein Bridge cicuits are suggested with temperature compensated amplitude, they use a pair of matched diodes or two diodes in close contact.

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FPGA / Re: Analog video output with FPGA ?

« Last post by Jaunedeau on Today at 08:16:00 am »

Well, are you sure you need 24-bit RGB to drive an old CRT TV anyway? I am not.

This is a good question. My idea was to start with 24bits on the prototype, then lower the bit-depth via software to see if I can reduce the cost and size (and soldering time/difficulty since the project might be open sourced if it works, and should be hobbyist friendly)

16bits RGB might be good enough, but at my current stage (just learning) prototyping with 24 bits won't cost more than prototyping with 16. Unless I go for and exernal DAC and can find a fast enough 6 bit one for cheaper (and with longer expected availability) than the dedicated 24bit video DACs.

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Projects, Designs, and Technical Stuff / Re: DIY Digital Caliper

« Last post by ali_asadzadeh on Today at 08:14:14 am »

here there are

https://github.com/MitkoDyakov/BluePillCaliper/tree/main/Hardware/Footprints%20-%20KICAD/CaliperPCB
https://github.com/MitkoDyakov/BluePillCaliper/tree/main/Hardware/Footprints%20-%20KICAD/CaliperBlade

Thanks for sharing, is there any updates regarding zero crossing?

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Projects, Designs, and Technical Stuff / Accurate sine wave in terms of amplitude

« Last post by sw_guy on Today at 08:05:26 am »

I am iterating options to generate accurate sine wave in terms of amplitude. Absolute frequency is not critical in this application.
There are few options and the first in my mind was AGC controlled wien oscillator. The main factor is temperature. Since the AGC is based on diodes, the "accuracy" of the circuit below is not even on the right map.


Another option is to use AD9833 (or equivalent) waveform generator chip. There might be better options in terms of amplitude accuracy, but the chip in question looks like be able to keep amplitude within 0.3% between 25 and 50C.

In practice, generating square wave accurately (still talking about amplitude) might be the easiest. Then it is matter of filtering to get sine wave. (and this time taken into consideration temperature impact to resistors and capacitors).

The target is to have 0.1% accuracy. To get there I am expecting to have stable enough generator + calibration.

sw guy

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FPGA / Re: Analog video output with FPGA ?

« Last post by Jaunedeau on Today at 08:03:36 am »

Delta-sigma modulation does not need such a high oversampling ratio. A 2nd order modulator with 2-level (binary) output has a theoretical SQNR of ~65dB with 32x oversampling, or ~80dB with 64x oversampling. For 5 MHz bandwidth, this would be 320 MSa/s (32x) or 640 MSa/s (64x). Maybe a little more if you want some headroom, but not 6GSa/s.

See also https://classes.engr.oregonstate.edu/eecs/spring2021/ece627/Lecture%20Notes/2nd%20&%20Higher-Order2.pdf

Thank you. My calculation was for PWM, I'm just trying to learn about PDM for my application and can't do the math yet. If 32MHz is enough, that might be done with SPI on a cheap STM32 or the PIO or an RP2040 and that would greatly reduce cost. But my understanding of PDM (and that would almost be the same problem with PWM) is that if I want to display a full 1/256 brightness line with a 16 oversampling, I would display first pixel as 1 followed by 15 zero, followed by 15 pixels all black (full zeros), making an average of 1/256, but meaning I would need a filter that averages the value over 16 pixel. I'd still get good micro adjustements if I output analog source or video from a camera (hence I don't need 256 oversampling for them), but in my case (pure digital source whed having a 1 pixel wide white ball on a black background is not uncommon) PDM won't be really better than PWM ? (and PWM would still need at least 2x oversampling, or alternance and black and white pixels would be hard to distinguish from continues line of mid-gray pixels) ?

Edit: How much SNR do you need for analog video? I guess hardly more than 50dB. So even 16x oversampling may suffice, but that's already borderline.

I don't now how to answer that question. I want a "clean" rgb video output for a very arbitrary definition of clean ^^

Btw, does the TV have RGB inputs, or do you need a composite video signal?

I an targetting TVs (and maybe later computer CRT monitors) that have RGB input only

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FPGA / Re: Analog video output with FPGA ?

« Last post by SiliconWizard on Today at 07:59:25 am »

Well, are you sure you need 24-bit RGB to drive an old CRT TV anyway? I am not.

8

Repair / Re: Mig welder wire feeder controller board not working

« Last post by .RC. on Today at 07:58:26 am »

I believe I have found the problem.  Could not work out why I could not get any of the DC voltages anywhere and why I could not get continuity to the isolation transformer from one of the AC input legs.  So I suspected it was a power supply issue.

Removing the isolation transformer revealed the problem.

9

Microcontrollers / Divide clock by 3 on a ATF16V8B

« Last post by Boomchil on Today at 07:56:48 am »

Hi everyone.

I would like to divide a clock by 3 using an ATF16V8B, to clean the video signal of a Sega Master System 2 (to bypass the division made internally which creates noise in the RGB lines). I only have ATF16V8B and I'm struggling to find the code or even the tools to do it (I'm on MacOS).

I have found this VHDL code : https://www.asic-world.com/code/vhdl_examples/divide_by_3.vhd so far but I can't find the tools to synthesis it to Jedec.

Can you please tell me if this is doable, and how could I do it ? I can access to a Windows computer if needed.

Many thanks for your help 

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Projects, Designs, and Technical Stuff / Re: Control of 2 CAN Open DS402 motors on a single shaft

« Last post by moffy on Today at 07:53:47 am »

Just to summarise, to see if I understand correctly, the slave motor is following the torque profile of the master(speed motor) but one sync behind, which is about 3ms, so you should be sharing the load roughly equally and the demand torque to the slave should reduce as the master motor approaches its set speed and its demand torque reduces. It sounds reasonable, what you could do to confirm it is log the current of each motor at the same time and check that they are load sharing during dynamic and static situations. What about when static, no speed change, does the master still provide a demand torque for the slave to follow?