Author Topic: EEVblog #532 - Silicon Chip Wafer Fab Mailbag  (Read 51805 times)

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Offline EEVblog

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EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« on: October 07, 2013, 10:06:47 pm »
A look at some equipment and wafers used in the manufacture of silicon chip wafers.
200mm and 300mm wafers, die, dice sawing, lead-frame manufacture, automated testing machine (ATE) probing, clean room bunnie suits, photo plots, BGA chip thermal test sockets, and the worlds smallest active FET probes at 100 nanometers for direct wafer probing!
Thanks to Vincent Himpe:
http://www.siliconvalleygarage.com/

 

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #1 on: October 07, 2013, 10:36:02 pm »
Okay, so how cool is it to get your hands on stuff like this?

Amazing... the die test rig alone is seriously impressive.  What do you guess... maybe a month to build one?

Vincent, thanks for sharing this!  :-+
 

Offline Jebnor

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #2 on: October 07, 2013, 10:47:19 pm »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!
Before this, there was a typo.
 

Offline walshms

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« Last Edit: October 07, 2013, 11:05:04 pm by walshms »
 

Online dr.diesel

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #4 on: October 07, 2013, 10:58:53 pm »
Vincent, thanks for sharing this!  :-+

 :-+

Offline walshms

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #5 on: October 07, 2013, 11:28:46 pm »
This video is from 2008, but gives a bit more insight into the beginning and some of the process:

 

Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #6 on: October 08, 2013, 12:15:32 am »
What happened to your finger at 10:50?
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Offline Greyersting

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #7 on: October 08, 2013, 12:43:36 am »
What kind of phone is that?
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Offline pickle9000

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #8 on: October 08, 2013, 01:30:42 am »
Dave what did it smell like?

Amazing mailbag, best ever for sure. Thank you Vincent
 

Offline EEVblog

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #9 on: October 08, 2013, 01:35:32 am »
What happened to your finger at 10:50?

Wasn't just the finger:
 

Offline nathanpc

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #10 on: October 08, 2013, 01:39:11 am »
This is by far the most fascinating mailbag ever.
 

Online free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #11 on: October 08, 2013, 01:46:53 am »
Well done Mate !

Now, if you think that probecard is an amzing piece of gear. Think about the test machine behind that sucker.
We have certain products that we ship over a million parts a day of. there's only 3600 seconds in an hour, 24 hours a day that's 86000 seconds.

you better get a machine that can execute that test lightning fast... even if you can do 3 chips a second ( these machines have multiple heads, one is testing the second on is unloading, the third one is loading... ) That's only 260000 chips a day. you need 5 of these testers ( assuming no downtime for maintenance ) to just run 1 product !

The cost of these machines is mindboggling. The really high end machines are actually not sold. There is no way to recup the development cost, other than to charge you for the test-time. You buy the hardware ( which cost multiple arms and legs) while the test software and the know-how is paid for by paying a price per second. If every chip costs 2 cents to test... and you run a million a day .. the bill at the end of the day is 20K$ ... 356 days a year. just for one product.
That is why only the really large companies can afford their own fabs. Everything else subcontracts it to the megafabs like TSMC and UMC or charters.

Some other mind boggling numbers:
The actual waferfab , the building, power, consumables, air filtration , electricity , gases and chemicals including the personell and the depreciation of the equiment in it costs about 600 million $ a year. And you have not made a single chip. so even if you are loitering for a minute ... 365 days at roughly 1.6 million $ a day ... or 68000$ an hour. Just to run that thing idle...

you cannot shut down any of that equiment. The process are so critical that the reactors need to stay in operation or you get all kinds o side effect inside the machine and the end result is chips that dont work right. So when idle we actually cycle 'dummy' wafers. put metal on , etch it off, put metal back on , etch it off. after 1600 wafer the reactors go down for cleaning... that takes 4 hours... so running dummies is mandatory but also very expensive as it eats into the cycle counter before mandatory shutdown.

A key machine going down is a disaster. maintenance is planned in conjunction with fab operations so that the downtime of the machine has no impact on the flow. they make sure there are no wafers waiting for that process step. there is daily, two daily, 3 daily, weekley biweekley monthley, bimonthly maintenance. The manufacturer of the equioment has checklists and these maintenances need to be done.

If the biweekly says : change all the bearings you change all the bearings. The biggest mistake you can make is looking at the bearing and saying 'but they still look good, ' That can get you fired... Nobody is willing to take the risk of leaving the bearings in to find out that 2 days before scheduled mainteance the thing comes to a grinding halt because the bearings wore out... now there are wafers waiting... if a biweekly maintenance means 4 hours scheduled downtime (nothing waiting) it only cost you the personell cost. if you have 4 hours downtime with wafers waiting the bill becomes over 250.000 $ ... there is going to be some yelling involved in that one... all for 400$ in bearings.

Right. some expansion on the video and elaboration.

image of a tester : http://www.teradyne.com/pressRoom/images/UltraFLEX-HD.tif (warning ; 43 megabyte file ! )
that testhead holds 1 chip under test ! if you ook inbetween the operator's arms you see the large plumbing fixtures that pipe liquid nitrogen into the head.. the chip is actually cycled , cold ( -30 degrees , ambient , 25 and hot (125) )

Now image a tester that tests 16 Gbyte flash chips.. Erase them , program checkerboard, read, erase , alternate checkerboard, verify, wipe, do this at three temperatures, finally format it lod the wear leveling algorithm , write the dead cell msrkers and allocation tables and spit it out.. That chips sits in the tester for maybe 50 to 60 seconds ... Now you understand why they cant make a sub 1 dollar flashchip... the testtime alone cost 2$. and thats not counting the cost of the machine, operators or building the machine sits in...

Bondout chip:
basically they bring out the internal data and address bus and the core is made 'static' ( the clock can be stopped) so that's ewhat the extre a pins are. this allows for the tracer to look over the shoulder of the core and look at the inside registers.
JTAG effectively eliminated bond-out parts

Leadframe:
the cup holding the die is flashed with a few microns of silver. a silver-eopxy glue is used to glue the die in the cup. after bonding and molding a stamping machine bends the pins and snips the shorting bar inbetween the pins and trims the pins to length.

Testsockets. The crowns on the pogo pins are made such that they cause only minimal dmage ot the ball but the sharp prongs cut onto the ball to guarantee good contact. also the bottom of the pogopin has a tiny crown. that construction is made sideways. so whenever you apply pressure there is a sideways wiping action cleaning the contact area between pogo pin and pad on the pcb.

Probeneedles
All those needles are used for manual probing on a probestation. we decapsulate prototype chips, solder them on a testboard and stikc it under a microscope. the probestation is just a large anti-vibration table. basically an air suspended massive block of granite with a board holder and floating microscope. micromanipulators have a grabber at the end. stick in a needled and you can position the needle above the die and pick off a signal. the microscope has a laser mounted that is used to destroy the passivation , or metal. so we can actually drill down and expose internal contacts. drop the needle and you can measure internal signals.

Bare dies. These are normal bondpads. i thought those were pillared but they arent. the Sawn silicon germanium wafer IS pillared. instead of bondpads there are solid copper rods sticking up. so these chips are not bonded . they are flipped upsided downon a flex and then ultrasonically rubbed until the copper rods weld into the flex substrate.

Mask. that thing is technically called a reticle. a real mask is chip-scale and exposes the entire wafer in one shot. as structures gotten smaller dust becomes a problem. so we make upscaled masks that are optically shrunk during exposure. the wafer is stepped a few chips at a time the black ring on the mask is used to put a celluloid foil over the mask. the masks are washed, dried , and then a fresh foil is applied. the distance between foil and surface of the actual pattern means, if dust falls on the foil, we can focus straight through that. it doesn't bother. That plate is pure microscope quality quartz. it is sputtered with chrome. The mask is actually for an plasma tv panel column or row driver. that's why this is a long skinny chip. its essentially a shift register with lots of output drivers. its got a lot of memory on board to compensate for panel deficiencies

probecard : the needles are made of a material called invar  http://en.wikipedia.org/wiki/Invar.
as this testing is done hot and cold we cant have the needleds extend or contract !. that would shift their position on the bondpads...
the tails are spot welded on the invar needle. then that golden (its actually kapton) sleeve is trimmed to length , slid over and the end tacked down.

The 8051 is actually a uPSD5000. it is a 8051 with a cpld ram and flash. it is the last generation ( or was. its discontinued) of the Waferscale PSD devices.

The big boy (300mm) is an image processor for HD lcd tv's. it takes the HDMI signal ,decrypts it and spits it to the panel drivers. it does upscaling , deinterlacing as well as the backlight modulation ( this is for LED panels where each LED is a RGB triplet that can be midulated independently )
« Last Edit: October 08, 2013, 02:20:37 am by free_electron »
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Offline EEVblog

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #12 on: October 08, 2013, 01:58:52 am »
The actual waferfab , the building, power, consumables, air filtration , electricity , gases and chemicals including the personell and the depreciation of the equiment in it costs about 600 million $ a year. And you have not made a single chip. so even if you are loitering for a minute ... 365 days at roughly 1.6 million $ a day ... or 68000$ an hour. Just to run that thing idle...

In our Seismic streamer manufacturing plant at my former company, we'd produce >$250K worth of product a day (more expensive than a new car these things).
So if a bit of my automated product gear broke down for an hour, you'd not only lose that money, but the customer has their survey boat sitting idle in dock costing then $2M/day in lost revenue.
So everyone had "standing orders" - no matter what you are working on, if production stopped, you dropped whatever it was and raced to production to fix it. I always had a pre-packed toolkit with all the right gear ready to go at a moments notice.
 

Offline kizzap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #13 on: October 08, 2013, 02:20:11 am »
An excellent video there Dave, thanks for sharing too Vincent.

There was one thing that piqued my interests, and it didn't seem to get mentioned. On the 200mm wafer, it looked like there were quite a number of dies that weren't the same as the rest of the batch. Is this normal, and what sort of purpose would it have?

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Online free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #14 on: October 08, 2013, 02:25:42 am »
those are parametric teststuctures.

there is a number of individual resistors, some loose diodes some loose transistors.
when we are depositing, for example, a resistive layer, that layer may not be the same thickness everywhere. having these teststructres allows a quick initial test. we simply measure the resistance teststructre and 'map' the thickness gradient across the wafer. if it is out of tolerance most likely very few parts will meet spec so we don't bother : simlply reject the entire wafer it's cheaper. so it is a kind of quick check to see if 1) nothing was missed (maybe a layer is missing) , 2) there are no crazy tolerances

Besides electrical structures there are also optical markers so the exposure units have calibration points for layer alignment.
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Online free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #15 on: October 08, 2013, 02:31:18 am »
Sorry bout the cleanroom overall size. that's all they had at weirdstuff warehouse. check the inside label. It'll say Agilent i believe. these came from the Lumileds fab ( Agilent -> avago ) here in san jose. So these were worn by some dude making your super bright led's in your overhead fixtures.
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Offline ChrisBoden

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #16 on: October 08, 2013, 02:40:15 am »
I love the shirt. ;)
 

Offline grego

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #17 on: October 08, 2013, 03:05:03 am »
Vincent, nice going.  Seriously.  Really interesting stuff.  Big +1.

 :-+
 

Offline JoeN

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #18 on: October 08, 2013, 03:40:53 am »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!


The guy got xylene and phosgene mixed up 19:48.  Dave is too smart to make this sort of mistake.  As a matter of fact, so am I.  I have to deduct 4 points right there.
Have You Been Triggered Today?
 

Offline gman4925

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #19 on: October 08, 2013, 03:42:23 am »
Favourite part
 

Offline marshallh

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #20 on: October 08, 2013, 03:55:32 am »
A+ great video. The probe head is nuts.

Got a board here not quite as thick but about 180-200mils or so (16 layers): yes they actually run 8mil mechanical drills through this aspect ratio pcb:

Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 

Offline EEVblog

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #21 on: October 08, 2013, 04:15:45 am »
Favourite part

Did you watch after the credits?
 

Online free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #22 on: October 08, 2013, 04:37:24 am »
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Online free_electron

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #23 on: October 08, 2013, 04:39:28 am »
I found this Talk about Fabrication by a guy who works in a FAB.    Really interesting.

It's an hour long, and oh so worth it!


The guy got xylene and phosgene mixed up 19:48.  Dave is too smart to make this sort of mistake.  As a matter of fact, so am I.  I have to deduct 4 points right there.
He got a whole bunch of other things mixed up as well. Like the order of processes, the way the implanter works and a bunch of other things. He doesnt work in a fab. He talked to people that does and he genuinely is i terested, but he's confused and mixed things up. That stuff is very comp,ex and it takes months before you start understanding the flow.
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Offline elCap

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Re: EEVblog #532 - Silicon Chip Wafer Fab Mailbag
« Reply #24 on: October 08, 2013, 04:54:04 am »
Thanks Dave and Vincent! That was a great mailbag, bring out some good memories.

I have used those Picoprobes a lot, measuring on wafers consisting mainly of passive structures. I had a big rack of all kinds of test gear, among other Agilent 4294A LCR meter an lock-in amp Perkin Elmer/EG&G 7280, and "home made" stuff. I especially remember when using the LCR meter I had problems with noise and had to make all cables as short as possible and also cut the Picoprobes down. It was easy with the correct tools, good microscope and sharp knife.
That's over 10 years ago now.. wonder what happen to all the test gear, would be nice to have some of it now.

And according to my experience silicone wafers are not that brittle. They will not just break without force, lifting them up is no problem. I used to cut them by hand. Use a diamond glass cutter to make a small mark/scratch that follow the crystal orientation (indicated by a flat end or a small cut out on the wafer).  Then tap on it gently and it will break in a perfect straight line.. if you are not unlucky to get some second grade wafer with undefined crystal orientation; silicone flying all over.
- NEVER handle wafers without wearing safety glasses, silicone is super sharp -

And probe cards.. almost has nightmare from them..  we used old probe stations that failed from time to time, resulting in all kind of problems, wafers flying, stacking many wafers on top of each other at unload (scratch!), and had the chuck lifted too high crashing in to the probe card! Fortunately the probe cards we used were not that complex so we could fix them in-house.
And all was just for R&D so just to tell the PhD dude; sorry, no results today, maybe tomorrow.

The foil put over the mask (over the black ring) is called pellicle. One other aspect of is also to protect the mask.

Wish I could send in some photo masks. They are a little bigger than 6inch..

 


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