flash: 0x001BA610 | packet 716: 0x12, 0xFF 0x8019CF82: 0xFF, 0x00,
flash: 0x001BA612 | packet 717: 0x16, 0x04, 0x58, 0x02, 0x0A, 0xFD 0x8019CF84: 0x04, 0x58, 0x02, 0x0A, 0xFD, 0x00,
flash: 0x001BA618 | packet 718: 0x70, 0x09, 0x01, 0x08, 0x28, 0x08, 0x5A, 0x3C, 0x03, 0x05 0x8019CF8A: 0x01, 0x08, 0x28, 0x08, 0x5A, 0x3C, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
flash: 0x001BA622 | packet 719: 0x30, 0x0C, 0x18, 0x1A, 0x1E, 0x14, 0x87, 0x29, 0x0A, 0x75, 0x77, 0xB2, 0x04 0x8019CF99: 0x18, 0x1A, 0x1E, 0x14, 0x87, 0x29, 0x0A, 0x75, 0x77, 0xB2, 0x04, 0x00, 0x00, 0x00,
flash: 0x001BA62F | packet 720: 0x14, 0x9A, 0x01, 0x11 0x8019CFA7: 0x9A, 0x01, 0x11, 0x00,
flash: 0x001BA633 | packet 721: 0x92, 0x01 0x8019CFAB: 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
flash: 0x001BA635 | packet 722: 0x27, 0x50, 0xA0, 0x94, 0xD5, 0x02, 0x08 0x8019CFB5: 0x50, 0xA0, 0x94, 0xD5, 0x02, 0x08, 0x00, 0x00,
flash: 0x001BA63C | packet 723: 0x14, 0x04, 0xA1, 0x55 0x8019CFBD: 0x04, 0xA1, 0x55, 0x00,
flash: 0x001BA640 | packet 724: 0x13, 0x8F, 0x62 0x8019CFC1: 0x8F, 0x62, 0x00,
flash: 0x001BA643 | packet 725: 0x13, 0x7F, 0x71 0x8019CFC4: 0x7F, 0x71, 0x00,
flash: 0x001BA646 | packet 726: 0x13, 0x73, 0x82 0x8019CFC7: 0x73, 0x82, 0x00,
flash: 0x001BA649 | packet 727: 0x13, 0x69, 0x95 0x8019CFCA: 0x69, 0x95, 0x00,
flash: 0x001BA64C | packet 728: 0x02, 0x24, 0x69 0x8019CFCD: 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
flash: 0x001BA64F | packet 729: 0x18, 0x0C, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0xFF, 0x01 0x8019CFF2: 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0xFF, 0xFF, 0xFF, 0xFF,
flash: 0x001BA65D | packet 730: 0x01, 0x11 0x8019D000: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
flash: 0x001BA65F | packet 731: 0x28, 0x10, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x24, 0x26, 0x28, 0x24 0x8019D011: 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x24, 0x26, 0x28, 0xFF, 0xFF, 0xFF, 0xFF,
flash: 0x001BA671 | packet 732: 0x49, 0x01 0x8019D024: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
flash: 0x001BA673 | packet 733: 0x01, 0x11 0x8019D02A: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
flash: 0x001BA675 | packet 734: 0x89, 0x90 0x8019D03B: 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
rsb r0,r0,r0, lsl #0x4
mov r5,r0, lsl #0x3
void main(void)
{
int iVar1;
undefined auStack568 [568];
sys_clock_init();
some_memory_stuff();
sys_init_uart0(BAUD_115200);
setup_timer_int();
sys_spi0_init();
fpga_init();
turn_off_brightness();
sys_init_display();
setup_display_lib();
tp_i2c_setup();
Your emulator work is interesting and impressive
I would never have tried to write one, it would have seemed too complicated a task (which it is, for me).
typedef struct tagARMV5TL_REGS ARMV5TL_REGS;
typedef struct tagARMV5TL_TRACE_ENTRY ARMV5TL_TRACE_ENTRY;
struct tagARMV5TL_REGS
{
u_int32_t r0;
u_int32_t r1;
u_int32_t r2;
u_int32_t r3;
u_int32_t r4;
u_int32_t r5;
u_int32_t r6;
u_int32_t r7;
u_int32_t r8[2];
u_int32_t r9[2];
u_int32_t r10[2];
u_int32_t r11[2];
u_int32_t r12[2];
u_int32_t r13[6];
u_int32_t r14[6];
u_int32_t r15;
u_int32_t cpsr;
u_int32_t spsr[5];
};
struct tagARMV5TL_TRACE_ENTRY
{
u_int32_t instruction_address; //Address of the traced instruction
u_int32_t instruction_word; //Instruction word for arm, half word for thumb
u_int32_t execution_status; //Information about if the arm instruction has been executed or not
ARMV5TL_REGS registers; //The 37 registers
u_int32_t memory_address; //Depending on the type of instruction this is set with the targeted memory address
u_int32_t memory_direction; //For load or store multiple instructions this signals if the given address is incremented or decremented
u_int32_t data_width; //For instructions that load or store half words or bytes this will reflect this, otherwise word width
u_int32_t data_count; //The number of words read or written by the instruction
u_int32_t data[16]; //The data read or written. Single instruction can do a max of 16 words
};
This means I have to implement a better tracing system. Already have some ideas about this. It will need an other program to read the trace data. The idea is to gather data for each instruction and write it in binary to a file. Already made a structure for it and support in the core code to allow for a circular buffer to be filled with trace data. Next up is add code to the instructions that load or store to or from memory.
Respect for your work! Would love to see your working methods.
0x8002FAA8 0xE92D4070 YES stmdb sp!, { r4 r5 r6 lr } r0:0x80857D4C r1:0x8019D464 r2:0x8019D45C r3:0x00000320 r4:0x00000000 r5:0x00000000 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8001933C r15:0x8002FAA8 cpsr:0x80000053 memory:0x81FF35A4 type:word count: 4 dir:down 0x8001933C 0x00000000 0x00000000 0x00000000
0x8002FAAC 0xE59F509C YES ldr r5, [pc, #156] r0:0x80857D4C r1:0x8019D464 r2:0x8019D45C r3:0x00000320 r4:0x00000000 r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8001933C r15:0x8002FAAC cpsr:0x80000053 memory:0x8002FB50 type:word count: 1 dir:up 0x8019D464
0x8002FAB0 0xE1A04000 YES mov r4, r0 r0:0x80857D4C r1:0x8019D464 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8001933C r15:0x8002FAB0 cpsr:0x80000053
0x8002FAB4 0xE595000C YES ldr r0, [r5, #12] r0:0x80857D4C r1:0x8019D464 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8001933C r15:0x8002FAB4 cpsr:0x80000053 memory:0x8019D470 type:word count: 1 dir:up 0x80857D4C
0x8002FAB8 0xE28FE030 YES add lr, pc, #48 r0:0x80857D4C r1:0x8019D464 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAB8 cpsr:0x80000053
0x8002FABC 0xE2801004 YES add r1, r0, #4 r0:0x80857D4C r1:0x80857D50 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FABC cpsr:0x80000053
0x8002FAC0 0xE5800038 YES str r0, [r0, #56] r0:0x80857D4C r1:0x80857D50 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAC0 cpsr:0x80000053 memory:0x80857D84 type:word count: 1 dir:up 0x80857D4C
0x8002FAC4 0xE580103C YES str r1, [r0, #60] r0:0x80857D4C r1:0x80857D50 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAC4 cpsr:0x80000053 memory:0x80857D88 type:word count: 1 dir:up 0x80857D50
0x8002FAC8 0xE2801008 YES add r1, r0, #8 r0:0x80857D4C r1:0x80857D54 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAC8 cpsr:0x80000053
0x8002FACC 0xE5800040 YES str r0, [r0, #64] r0:0x80857D4C r1:0x80857D54 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FACC cpsr:0x80000053 memory:0x80857D8C type:word count: 1 dir:up 0x80857D4C
0x8002FAD0 0xE5841014 YES str r1, [r4, #20] r0:0x80857D4C r1:0x80857D54 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAD0 cpsr:0x80000053 memory:0x80857D60 type:word count: 1 dir:up 0x80857D54
0x8002FAD4 0xE5D01011 YES ldrb r1, [r0, #17] r0:0x80857D4C r1:0x00000000 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAD4 cpsr:0x80000053 memory:0x80857D5D type:byte count: 1 dir:up 0x00000000
0x8002FAD8 0xE2850024 YES add r0, r5, #36 r0:0x8019D488 r1:0x00000000 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAD8 cpsr:0x80000053
0x8002FADC 0xE7900101 YES ldr r0, [r0, r1, lsl #2] r0:0x00000000 r1:0x00000000 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FADC cpsr:0x80000053 memory:0x8019D488 type:word count: 1 dir:up 0x00000000
0x8002FAE0 0xE590100C YES ldr r1, [r0, #12] r0:0x00000000 r1:0x00000000 r2:0x8019D45C r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAE0 cpsr:0x80000053 memory:0x0000000C type:word count: 1 dir:up 0x00000000
0x8002FAE4 0xE5912030 YES ldr r2, [r1, #48] r0:0x00000000 r1:0x00000000 r2:0x00000000 r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAE4 cpsr:0x80000053 memory:0x00000030 type:word count: 1 dir:up 0x00000000
0x8002FAE8 0xE2841008 YES add r1, r4, #8 r0:0x00000000 r1:0x80857D54 r2:0x00000000 r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x8002FAE8 cpsr:0x80000053
0x8002FAEC 0xE12FFF12 YES bx r2 r0:0x00000000 r1:0x80857D54 r2:0x00000000 r3:0x00000320 r4:0x80857D4C r5:0x8019D464 r6:0x00000000 r7:0x80192E6B r8_usr:0x80000E48 r9_usr:0x81000000 r10_usr:0x80192E9C r11_usr:0x80192E9C r12_usr:0xFFFFFFFF r13_svc:0x81FF3598 r14_svc:0x8002FAF0 r15:0x00000000 cpsr:0x80000053
main XREF[1]: prepare_for_main:800001a8(c)
80035320 8e df 4d e2 sub sp,sp,#0x238
80035324 00 00 a0 e3 mov r0,#0x0
80035328 3e cb ff eb bl sys_clock_init void sys_clock_init(void)
8003532c 54 08 00 eb bl some_memory_stuff void some_memory_stuff(void)
80035330 20 01 9f e5 ldr r0,[BAUD_115200] = 0001C200h
80035334 58 cb ff eb bl sys_init_uart0 void sys_init_uart0(uint baudrate)
80035338 2a cb ff eb bl setup_timer_int void setup_timer_int(void)
8003533c 72 bf ff eb bl sys_spi0_init void sys_spi0_init(void)
80035340 56 85 ff eb bl fpga_init void fpga_init(void)
80035344 14 9d ff eb bl turn_off_brightness void turn_off_brightness(void)
80035348 a1 a0 ff eb bl sys_init_display void sys_init_display(void)
8003534c f2 8f ff eb bl setup_display_lib int setup_display_lib(void)
80035350 7d 89 ff eb bl tp_i2c_setup void tp_i2c_setup(void)
void setup_mmu(void)
{
uint baseaddress;
baseaddress = 0x80730000;
setup_mmu_trans_table(baseaddress,0x80000000,0,0,0,0,0x80000000,0,0);
setup_mmu_trans_table(baseaddress,0,0x80000000,0,0x80000000,0,0x80000000,0,0);
setup_mmu_trans_table(baseaddress,0x80000000,0x80000000,0,0x80000000,0,0x2000000,0,3);
mmu_set_base_address(baseaddress);
mmu_clear_wb_tlb();
mmu_set_domain_access(1);
mmu_enable();
mmu_instr_cache_enable();
mmu_data_cache_enable();
return;
}
void setup_mmu_trans_table(uint baseaddress,uint param_2,uint param_3,uint param_4,uint memaddress,uint param_6,uint param_7,uint param_8,uint cacheable)
{
uint uVar1;
uint uVar2;
uint uVar3;
uint uVar4;
bool bVar5;
uVar2 = param_3 >> 0x14 | param_4 << 0xc;
uVar3 = memaddress >> 0x14;
uVar4 = param_7 >> 0x14 | param_8 << 0xc;
uVar1 = param_8 >> 0x14;
while ((uVar1 | uVar4) != 0)
{
*(uint *)(baseaddress + uVar2 * 4) = uVar3 << 0x14 | 0xc10 | (cacheable & 3) << 2 | 2;
bVar5 = uVar4 == 0;
uVar4 = uVar4 - 1;
uVar1 = uVar1 - bVar5;
uVar2 = uVar2 + 1;
uVar3 = uVar3 + 1;
}
return;
}