What these 83E8, 83E9 means ?In principle they are expansion stage numbers, e.g. on the slower/cheaper
models (Tekway DST4000, DST3000) they marked as 83ED, 83EE, 83EF, 83F4 and 83F5.
The firmare (dso.exe) is reading back these number during startup from FPGA register
and changing DSO features to what they should be for specific stage number.
These are, afaik, sample rate, memory depth, filters, equ sampling, avg sampling.
For the DSOs in this thread (Handheld and Benchtop) there are two expansion stage
numbers, 83E8 and 83E9.
Even if most ppl recognized the 83E9 since i think Nov 2011, they were available from the beginning.
The first "fast" 83E9 version was already in Dec. 2009 available, however with sme bad as trigger issues,
so Tekway downgraded DSOs to 83E8. Later Hantek tried to pimp up the mainboard and the FPGA design,
the result was a disaster model hw 1005 and very unstable FPGA/firmware.
Finally the issue was solved and with hw1007 in Nov 2011 the "fast" FPGA design version was rolled
out to production DSOs. The hw 1007 83E9 FPGA design is however very hard on limit, to fix a littlebit
the skew is no room anymore, an FPGA overclocking is not possible as well (max cloc in 105MHz).
With older, but slower, FPGA design 83E8 the FPGA was working with no issues with 125MHz input clock,
giving max sample rate of 1,25GS/s
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If you wish to test/play arround with available FPGA design, see attached file.
I've only included the official production versions, there are few test versions as well
but i don't think they really important.
WARNING - if you own hw1005 DSO remember that your DSO is already unstable and will probably
not like any FPGA deisgn changes.For the benchtop B/BM/BMV models in folder DST1000B there are:
dn_hw0_83E9_date_091201.rbf (very first "fast" FPGA design for DST1000B)
dn_hw0_83E8_date_100224.rbf (the first "step back" version)
dn_hw1005_83E8_date110225.rbf (a complette Hantek hw1005 disaster)
dn_hw1005_83E9_date110423.rbf (... bit updated disaster)
dn_hw1005_83E9_date110427.rbf (... and finaly the only stable version for hw1005)
dn_hw1007_83E8_date110522.rbf (back to the root)
dn_hw1007_83E9_date111122.rbf (first stable "fast" version 83E9)
For low cost models Tekway DST3000, DST4000 series and the Hantek DSO5000C (which i think didn't exists anymore)
you will find a subfolder "DST3000_4000_models" in the attached file. Remember, these designs are NOT compatible
with DSOs from this thread, meaning Tekway DS1000B and Hantek DSO5xxxB/BM/BMV. I'm attaching these
files only for test purpose/testing.
I've included as well design from Handheld Hantek DSO1xxxB/BM/BMV
dn_handheld_hw1001_83E8.rbf
This is, from the point of skew between ADCs (bug 6 in the bug list, see attahement in the first post of this thread)
the best design ever - however it is 83E8 version only and it requieres on Benchtop to execute factory calibration
(not self cal !!!) to work properly with trigger. This is due different skews and trigger circuit.
Vice versa you can use benchtop designs on handhelds as well, however you need to execute factory caibration as well.
EDIT: I've added as separte attachement the FPGA design from MSO models.
dn_MSO_83E9_date111123.rbf
It seems to be never than the latest DSO 83E9 version, it is for sure compatible with B/BM/BMV benchtop models.
To use with handheld it require additionaly factory calibration. As far i think the only difference to
dn_hw1007_83E9_date111122.rbf design is clock out/enable from FPGA (K9, F6) to I/O header, which of course
have no function as long there is no LA board added. I haven't tested it deeper, no time for that now.
How to install? Simply copy to flash drive from there to root fs of the DSO as dn.rbf, e.g.
cp /mnt/dn_hw1007_83E9_date111122.rbf /dn.rbf
delete then /param/sav/run* and reboot the DSO.
After that run self calibration (at least, see notes above if factory cal necessary as well), this will synch the
firmware t the FPGA design.