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Good to know about the battery.
.I bought the bigger Metcal after using the smaller for a few years, and I was expecting more too.
Maybe it is the tips - given these actually set the temp.
A lot of generated clocks, as BrainHG say. In this form it will not work. You need to recreate all RTL based on logic of original schema, but made if fully synchronous. You can use PLL to boost original 8MHz clock to some high frequency clock to have a room for maneuvers, it definitely will help (ratio of speed of original circuit and speed of MAX FPGA will allow using of a LOT of ticks to implement logic that originally would be fit in one tick).
But it is not an easy task.
Alternatively you can try implement original schema, using low level primitives of FPGA and disabling optimization in synthesizer, but it quite hard and do not grantee resultTiming of FPGA primitives is different from timing of original logic.
Maybe we'll get to see something from Dave.
For the PLL, what you want is a simple PLL, 8MHz in, 8MHz out.
It is the output phase you want to adjust.
Something like +/-45 degrees, or 90 degrees.
Remember, you want the PLL source clock to be a dedicated clock input pin.
Then, the output of the PLL should feed the verilog source code's input.
Originally I assumed you had your own verilog source module which was wired to the IO pins, which was wired to the source module you provided above. This was where I thought you were inserting your custom PLL or LCELL logic. Without having your own middle man module, I see how you may have difficulty adding your own middleman logic buffers, delays, inverters, or anything other logic you might be trying to add as a max10 is a little overkill for the provided logic.
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