FPGA

Two Frequency Dividers on a GAL16V8

FPGA based unknown circuit application

Gowin IP simulation

« 1 2  All »

Poor man's FPGA DAC

Kria SOM Carrier with Dual FMC?

Texas Instruments Bipolar TIBPALs Programming Algorithms

ICE65 software (ICEcube2 Version 2012-03) for ICE65L04F-TCB132C FPGA

Using ULPI USB PHYs for custom data links

« 1 2 3  All »

Gowin GW1NSR-LV4C - using CM3 with HperRAM ref design

How to read data in Verilog at a particular clock edge?

Vivado: Synthesis crash (address violation) at "Start Cross Boundary" stage

In Verilog, is it possible to define XXX only if a parameter is set?

Need a really dumb PC/Win RS232 terminal program.

BUFGMUX glitch-free behavior

How to use FIFO to process fast ADC data

Help Please: (Virtual) JTAG Interface - data transmission

WTF Xilinx

« 1 2 3 4 5  All »

DINI Group DNV7F2A

Verilog Floating Point Clock Divider Release.

Video Upscaling and Overscan

Used Bittware board

Input signal synchronization

Long time since I've played with PLD's.

Gowin M3 CPU usage with FPGA fabric

Help with converting old PALs to GAL

Schematic for old QMTECH Zynq XC7Z010 Starter Kit

New Zynq based SOM

Good intros to FPGAs?

« 1 2 3 4  All »

newb question

SoC as alternative to STM32H7

« 1 2  All »

Turn off name mangling during Vivado behavioural simulation

Playing with old XC3000A + XACT 5.2.1... no pins assigned or routed

How to download ispVM System software version 17.7 (or later)?

Forcing usage of clock enable in MAX7000 CPLDs

Looking for instant on FPGA or CPLD for a current project

Reading a file in Verilog

The NEORV32 Risc-V Processor

« 1 2  All »

Verilog right shift help

FPGA high speed UDP stream and packet drops on PC

« 1 2  All »

Designing a FPGA board for a 90s SPARCstation...