FPGA

Renesas SLG46826 GreenPAK SPLD, what are the three memory regions used for?

Intel/Altera - DDR3 megafunction fails in Quartus 20.1.1

Suggestions for a dev board for learning some FPGA things

Need help writing to XDMA

Vitis 2023.1 would fail to compile when I add a custom IP

Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM

PALCE Chips

Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10

Quick checking for VHDL syntax

No pulse in CLK test points

Port pins missing in Debug net list

Low budget FPGA needed

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ATF15XX Dev DK2 example file PLDs etc

NEORV32 (RISC-V) soft-core "coremark" result

AMD/Xilinx announced their own RISC-V soft-core

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Has somebody tried TCL scripts with "Gowin EDA" (Gowin FPGA Designer)

xilinx Z7 (7Z045) control chip warms up quickly at boot time

NEORV32 soft-core CPU (RISC-V) - bootloader is not working

FPGA Bluetooth Project

Pmod BLE Module with MCU

Successfully constraining paths in (old) Quartus

FPGA Question.....

How to describe a 74HC74 as part of a Spartan-6

Issues with git cloning repo with "RISC-V RV32IMC Toolchain"

VHDL exponential operator (**) works for synthesis?

FPGA Nexys A7 100T Board with PMOD ESP32

inout with physical pins in Verilog

why I get BAD PACKET ERROR?

PMIC for Z7020

BGA Confusion

Intel to spin off FPGA biz

Cordic on verilog

UART rx is not properly working

Mixing DDR3 data lines between bytes

Why wide demux allows the partitioning of memory bandwidth to be able to change

Faster FPGA compilation times using... FPGA? GPU?

Microblaze 64 bit

help on choice programmer JTAG

FPGA bargain on Ebay

Zynq DMA Scatter Gather still included when disabled...?