FPGA

Strange location of configiration pins on all Cyclone FPGA

Problem in Generate

ICE5LP4k SG48 voltage feeding through IO pin 48

Verilog Simulation Testbench timing output async events.

Intel replaces their NIOS II soft core in their FPGAs with 5x faster NIOS V RISC

ACAP Real prices

Xilinx Spartan 3A availability

work around VHDL's lack of a preprocessor

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SERDES pronunciation?

ALU in MIPS

Vivado for Windows, what do I need

Xilinx DLC10 Platform USB cable

Measuring On-chip resistive termination (impedance adaptation)

FPGA IO - parallel termination resistors

Interfacing a DE0 Nano (EP4CE22F17) with at FT232H as a usb to fifo.

HDMI / DVI encoder, with audio, smart Quartus PLL integration, in SystemVerilog.

SystemVerilog Example Testbench which Saves a .BMP picture and executes a script

Trying to workout `ifdef syntax to assign a specific localparam in SystemVerilog

FPGA LVCMOS vs LVTTL standards

Xilinx project with USB (ULPI PHYs)

FPGA Benchmarking algorithms

1Gb Ethernet core

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FPGA Damaged

Changing an attribute in a LOGIC declaration based on a parameter.

Ring Oscillator to determine delay

Xilinx Transceivers

Cmod A7 driving some DACs

Where to start with FPGA PCB design?

PWM output with Spartan 6 OSERDES2

Configuring Multiple Xilinx FPGAs From 1 SPI Flash?

Ring Oscillator on an fpga

Very small linux capable core

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Techniques to measuring propagation delay of FPGA routes

MachXO2 FIFO_DC - are clocks really independent?

Which HDMI serializer chip to use for small fpga design?

Microblaze vs Zynq vs Zynq ultrascale+ applications, examples?

Xilinx Artix 7 Bitstream Encryption Fix?

Any good beginner ideas for teaching?

Implementing old PAL/GAL into HDL

RS-232 on ice40 UP5k