FPGA

Xilinx Kria SoMs

STA timing closure for asynchronous FIFO

TL866II+ - what to select to program PALCE22V10H ?

Help, how to program TMS32F2812GHHA

Python Modules/Libraries?

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LDPC soft decoding - a breadcrumb trail for others.

Hacking surplus Pano Logic thin clients

Basic Serializer Verilog

Address decoder

What is the proper way to invert and tie high/low, signals in the Vivado IP inte

VHDL Code to Verilog Code

Pixel to byte

FPGA project where clock for it is external signal - what rules for designing?

CSI-2

WTB cheap low-end evaluation board and cables

[Solved] Cyclone V (de10-nano) SDRAM controller - how to reserve memory for FPGA

Why does this dds code fail (Solved)

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Quick question on Quartus support

Inferring block RAM

EPM240T100C5N -> Fitter requires XX LABs to implement the project but the device

What is a better write enable

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High speed bidirectional MPU interface

Timing issue.

Specific to the group but slightly off topic

GOWIN FPGA

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Gowin MiniStar Nano Limited Edition

Any tutorial on AXI PS-PL interop for the latest version of Vitis?

FPGA output not consistent with ModelSim

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Looking for Xilinx Foundation 2.1i, 3.1i software.

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HDL Code formatting.

Waveform generation on FPGA

8-bit retrocomputer: MMU + VIA from a PLD: ATF2500C-20PU?

How CORDIC sin/cos in HDL works.

Sine Wave on FPGA

low-jitter timing generation using FPGA

FPGA based I/Q generator

FPGA failure modes

PALCE programming algorithm

True Dual-Port memory verification

Interfacing LVDS laptop screen with fpga