FPGA

Efinix FPGA design sometimes a signal is not set high...

[ANNOUNCEMENT] Apio support for Gowin FPGAs is available for testing.

Integrating a Custom DCP into a Vivado Project

Spartan-6 -- safe to provide VCC_AUX and VCC_IO only?

ECP5: Setting Vref off recomended limits. Any experiences?

Advice for my graduation project

[SOLVED] EPM240 and boundary scan

Reading a 16L8 PAL / question on early SRAM card

problem with AXI bus

ECP5 SPI flash programming using open source tools

Ise Would not detect XC6SLX45

Anyone using Xilinx XC2k XC3k XC4k FPGAs?

where to get prehistoric SW for earliest (PALCE&GAL) PLDs ?

Mixing verilog and system verilog?

(book) Pipelined Multi-core MIPS, Implementation and Correctness

New TI tiny PLDs (TPLD)

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XC9500XL : using "Timing driven" macrocells power setting

FPGA beginner: I2C slave

Re-programming Secure Microchip ATF150x series CPLD devices

Salvage board for sale on ebay

My first FPGA (MAX10) design : some questions about clock and other aspects

building analog devices ADC HDL examples

Trying to create accelerator with vivado + SDK

JESD204B over fiber

Lattice XO2 clock pins/signals

JESD204C over Optical Fiber

Searching for Launch Diagun firmware from EPM240 Chip.

does exist a mirror of ftp.altera.com?

Xilinx/AMD Artix-7 Memory and FIFO Verilog Models

Xilinx MPSoC and RFSoC, what is the big deal?

New service to rent and trade-in FPGA, RF and AI boards! (US only)

True HDMI for Tang Nano 9K

Xilinx/AMD Artix-7 Memory and FIFO Behavior

Vivado (Xilinx) - Is there a way to store project information on GIT?

SRAM timing

How modeling static RAM in Verilog

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Lattice CrossLink FPGA configuration using I2C

Modelsim Altera Edition 6.4a from Altera Quartus II 9.0

Small footprints with 'many' min 12G tranceivers

Help with my first IIR biquad (DF1)