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Here in the forum I already showed some ideas and parts of an µC controlled multi-slope ADC.
https://www.eevblog.com/forum/projects/multislope-design/
So here I finally show my multi-slope ADC version as a "complete" project in a separate thread. The hardware side is essentially finished, with still a few resistor/capacitor values to tweak. The board is a little more than just the pure ADC. It also includes the reference (LM399 or LM329), a buffer amplifier and MUX for the input. So it is a limited (only 10 V range with little protection) voltmeter without the display part. Currently a PC is used for display and saving the data. Power is from a 2x18 V (2x15V is likely better) transformer. The 5 V part could use a lower voltage (currently just series resistors).
The software is currently supporting the basic functions including the MUX and a few debugging function. The ADC part sends out raw results via optically isolated UART and the ground referenced side (PC) is doing the conversion to the final result.
The hardware side is relatively simple, with an µC (Atmel Mega48) for control, xx4053 switches and 7 OPs. For the performance mainly 1 OP and 6(7) of the resistors are important. However even with simple parts (e.g. TL072 OPs for the integrator and 100 ppm/K resistors) the circuit works surprisingly well. The OPs given in the plan are the ones currently used.
The circuit shown is a slightly simplified version of the test board - leaving out alternative and optional parts and the ISP connector. I know the plan is not easy to read - sorry for that.
The optional extras on the board are other resistor / reference foot prints, alternative canned oscillator, a few more caps, a LM393 comparator to detect overflow, an input buffer before the MUX for 1 channel, a simple current source and an optional buffer for the ground return current at the ADC.
From the hardware side the ADC is a little similar to the HP 34401:
- switching via xx4053 at the integrator input. Here using 74LV4053 as a slight upgrade.
- a 2 OP integrator (essentially standard), but with more modern OPs.
- using a µC for the auxiliary ADC, though a more modern one with integrated memory.
- using continuous integration instead of a reset of the integrator. Instead of starting from zero the initial and final charge is read by the µC internal ADC.
Different from the 34401, there is no ASIC and the control is directly from the µC. The main difference is that my version also includes a more classical rundown phase and this way reaches a higher resolution and in part due to the more modern OPs a lower noise. So the ADC is in between the classical multi-slope ADC like used in the Keithley 2000 and the continuous integrating variation of the 34401.
The software side is a little tricky, as the program uses the program speed for timing and thus is written in ASM with careful check for the timing. However it is only the actual conversions that are so time critical. So the time critical parts are essentially ready.
Besides the actual ADC conversions, quite some code is there for 2 internal calibration measurements. One is to measure the ratio of the reference currents. The other is to measure the scale of the µC internal ADC relative to the reference currents. With measured ratios there is no need for special and accurate resistor ratios, except 3 reasonable (e.g. 1%) equal resistors for the integrator input.
The PC side program is currently written in Turbo Pascal. The software assumes a build in RS232. So for modern PCs it would need to be rewritten, e.g. to support an USB to UART bridge. The functions are not that complicated, and even a simple µC like the AVR should be able to do the job (though it would help to have a 2nd UART or USB interface).
Despite the simple hardware (about as simple as a good multi-slope ADC can be) the noise of the ADC itself is quite low. Currently I get a little below 1 µV RMS for 1 PLC auto zero readings, good enough for 7 digit resolution and often more limited by the reference.
Compared to a normal DMM the input MUX (DG408, optional DG508) has quite some leakage currents and there is not much protection. A practical voltmeter would need either a lower leakage mux, an amplifier instead of the buffer and more protection. An alternative extension is an additional amplifier (AZ) and protection stage in front of the board - this is more like the intended extension of the board. The ISP connector could also be used to control such a front end.
So far I have only done a partial linearity test. The result looks promising, with low local linearity errors. However the test does not include all INL sources (especially thermal effects) and is not sensitive to a more smooth background, e.g. a square or cubic contribution. A full INL test is still open.
So far I don't see a reason why linearity should be much worse than the 34401, except for the resistors currently used.
So the choice of resistors can be a topic if really good linearity and stable gain is wanted. The test data shown below are with not so good resistor matching, leading to a gain drift of some 12 ppm/K. I consider this bad luck for 15 ppm/K class resistors - it was better before, with simpler resistors.
The current board has a few bodges, but not that many.
While basically running there are still a few parts unfinished or open to improvements:
- better decoupling / ground routing (especially better EMI tolerance)
- optional parts on the board (e.g. comparator for overflow )
- speedup of the rundown from currently some 200 µs to maybe some 60 µs.
- use better resistors for low INL (U³ part) and gain drift
- faster conversion mode like 1 ms (needs fast UART interface, maybe shorter data format)
- accurate adjustment of integration time for better hum suppression
- control for external front-end
- PC software: change to C (with a µC) or Python (for the PC or Raspberry)
The attached files are:
1) Circuit diagram (simplified)
2) ASM code for the AVR + Pascal code for the PC (ziped)
3) Plot of data: relative size of reference reading versus diode voltage as a temperature sensor.
The data are dots with 20 ms integration each, during warm-up for some 15 minutes.
4) Head of sample data file (with some added comments)
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Awesome project.
How do you perform an INL test?
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The INL test is a difficult part. For the final test I would have to send a unit to someone with suitable high end gear (calibrator and 8 digit DMM).
The tests I can do are in 2 steps. The first part is testing for possible fine wiggles in the INL curve: I have programmed the ADC to use 2 different versions of the run-up, by using a different modulation frequency. This shifts most of the short range INL errors to a different voltage level. Than a slowly changing voltage is measured with both modes. Ideally both versions should give the same result. Due to charge injection from the switches and similar effects, there is a small difference, that should be constant. So the different of the 2 modes is a good and quite sensitive test for those possible fine wiggles in the INL curve. I did quite a few such test, especially with an older version that had a not so good run-up part and here the test did show some problems over a rather local range. The newer run-up version essentially solved that problem.
This test is a little unusual and requires the direct control of the ADC, but it is fast and low noise, so it can resolve even small errors (e.g. < 0.1 ppm range) without special gear. As both readings are with the same reference, it is not sensitive to reference noise and drift. I still have to repeat this test on the new version with a little more resolution / averaging and over a larger range.
A crude first test of this type could also be done by just looking at the discharge curve of a large cap: while not always perfectly following an exponential, it should be reasonably smooth, and local INL errors or DNL errors would show up as deviations from a smooth curve. Attached is such a measurement: the horizontal axis is the voltage with some -400 mV offset and 42 µV steps (ADC internal units = clock cycles worth of the negative reference), the vertical scale is µV. These are raw data in an non AZ mode. The voltage range (around 1:1 PMW) is where the older run-up version showed errors in the 50 µV range. In this range also DA related errors would show up, as the average integrator voltage changes quite a bit. So DA is not a significant issue here.
The second group of tests to do is still open. The main INL part to look for is the smooth long range part, like U² and U³ contributions. A first test is the so called turn over test, using an external isolated reference and measure this with both polarities. This kind of tests the even powers. For the odd powers one would need to add an offset, or use more test points and measure differences, checking that the sum of 2 voltages is measured right. This test requires stable and low noise reference for both the ADC board and the external ones and also thermal EMF can cause quite some extra errors. So while only a few test points (e.g. 10) are needed, this test is not easy and fast. Here a high end calibrator would really help.
Before doing the INL test I have to fix the drift problem - so replace the resistor(s). It looks like one is bad (too high TC).
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I've been following the other thread, and I can see that a lot of work has gone into this. It's very cool to think that we could build our own equipment to this level of performance, especially if we have a task which requires extreme precision but not the full gamut of a high performance multimeter.
Do you think you could make a brief comment about which parts of the circuit do what? -
A few comments on the circuit parts:
The upper left corner part (OPs IC8,IC9) of the circuit is the reference part, with amplification to some 14 V and -13.3 V. The circuit has not much special. Different from many DMMs, there is a little filtering for the reference, as higher frequency noise (some 50 kHz) can contribute to the noise. It is a little unusual that the voltages are not symmetric - both references together are used as an effective 0.7 V level for a smaller slope rundown step.
The power supply part is just normal +-15 V and +5 V from linear regulators, for dual 15-18 V / 10 V AC (mains or maybe switched mode).
The OPs IC11 and IC2 form a 2 OP integrator, to get a really low voltage at the input. The 2 OP integrator is pretty much standard.
Here IC11 (OPA1641 used, could be OPA145 later) is responsible for the low frequencies (up to some 1 MHz). This OP is the one that needs to be low noise, as the noise of this OP is about amplified by a factor of 2.
The OP IC2 is responsible for the higher frequencies and less critical, it just should be fast. C17 and R20 are there to help with settling of the integrator - the suitable values depend on the OPs used and maybe the parasitic capacitance. C37 is there in commercial circuits - I did not find it helpful, so not populated, but I kept it there just in case. It may be needed if IC11 is a BJT based OP. R10/R11 are effectively reducing the speed of IC11, the right value depends on the OPs used.
The supply for the integrator is isolated via R31/R32, so that at least the AC current flows back mainly through C6 and C14 and thus a controlled path. As an alternative to C6/C14 I have tested a ground buffer (a little like used in the Keithley 2002), that is also powered from the same supply island - but it did not give much difference. So c6 / c14 are just the simpler way.
The 4053 switch, very much like in the 34401 switches the currents to the integrator. They go either to ground through R35 (ferrite bead) or the integrator. Different from the 34401 I have separate control for the 3 switches and make use of it. As the input current is send to ground or a virtual ground at the integrator, there is no problem to use a low voltage (5 V) CMOS switch even with +-14 V of input voltage and reference. The switches work essentially at zero level. The resistors R1,R2,R3 are the ones I had bad luck with (R1, which is the most critical one has to high TC). Self heating of R1 can be one of the major factors effecting the INL. So in the final version this would need to be a good one (e.g. wire wound or foil or resistor array with R2,R3).
An amplifier like IC4 (NE5534) is called slope amplifier and usually has only 2 diodes (no D10) in the feedback. It amplifies the integrator output voltage around zero and has the diodes for clamping the voltage. The output of IC4 is between some -0.6 V and + 1.2 V. D10 and R23 result in a relatively linear range from about 0 to + 500 mV.
The output of IC4 goes to the µC internal comparator with R40 and R34 for level shifting. This is the "zero-crossing" comparator used for run-up and run-down.
R15 sets the actual trigger level for the comparator.
The OP IC13B gives another amplification of about -20 and has an output limited to 0-5 V that goes to the µC internal ADC.
As the µC internal ADC is slow, it is used with the integrator in stop mode. So IC13B does not have to be very fast - the limited BW may even help.
IC12 with the transistors is an buffer amplifier with bootstrapped supply (currently the bootstrapping part is not yet used). The circuit should work this way, but it might be better to change the lower side of D9 a little. The bootstrapping helps to get very good linearity from a buffer, as the OP sees an essentially constant common mode voltage. The OPA145 was chosen here because it is low noise, reasonable fast and still low current consumption. The heat from the buffer amplifier is a possible source of INL. -
Could you elaborate a bit on the mechanism with the rundown and residual ADC measurement, plz?
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A few more details on the control-sequence:
Besides the classical multi-slope with rundown, there is the continuous integrating ADC variation (e.g. 34401 and newer), see US Patent 5117227 (1991).
These ADCs don't use a rundown and integrator reset. Instead they measure the charge in the integrator with an auxiliary ADC, both at the start and at the end of a conversion. The net charge added during the phase in between is proportional to the difference. This avoids the time lost in the rundown, so it can be a good idea at high speed. If the initial charge is sufficiently accurate measured, there is no need to reset the integrator.
The scale factor for this auxiliary ADC depends on the value of the integration capacitor and resistor and is thus not very stable. This limits the useful resolution for the auxiliary ADC to some 8-12 Bit. For high resolution more resolution is needed before reading with the auxiliary ADC. Classically this is with very high modulation frequency, but this path is kind of limited and difficult.
My ADC uses an additional rundown phase to get the extra resolution. This is much like in the classical MS-ADC: the input is disconnected and the references are controlled (still through the µC) from the comparator signal. In my case it is first the stronger, positive reference (for at least 1µs, even if the integrator is already negative), than the negative reference and finally both reference together for a smaller slope. After these 2 steps of classical rundown, the small rest is than read by the µC internal ADC.
So the auxiliary ADC is not to replace the rundown, but only to support it and replace the reset phase.
As the resolution is very good (1 LSB corresponds to some 10 µV at the integrator), there is no more need for a reset. As only the difference between 2 readings of the auxiliary ADC enters the amplifier does not have to be DC stable. Even if one would use a reset (e.g. for a triggered measurement), one would still use the initial reading as the zero-point of the auxiliary ADC.
The rundown and ADC reading can still be reasonably fast: some 60 µs for the actual rundown, some 20 µs waiting for amplifier settling and some 20 µs for the ADC sampling are really needed. Currently there is a separate reading for the end and start and sometimes additionally an auxiliary reading from a different channel (e.g. for temperature). In the classical form the reset phase often takes quite some time - often more than whatI need for the ADC reading.
Overall the resolution is about 10 bits from the run-up, 10-11 bits from the run-down and some 7-8 bits from the µC internal ADC. So there is plenty of nominal resolution so that quantization-noise is not an issue, even down to some 1 ms integration time. It is normal that the final reading of the µC internal ADC is a little noisy - the full resolution is for the internal calibration and possibly future short integration time.
For the run-up part I now use a simple 3 step pattern, a positive, a negative and a variable (depending on the comparator) phase. This is a little like what is used in the 34401 and 3458. The early version with a 4 step pattern (2 variable phases like in US 5200752) did not work well. For some reason there is a tiny difference between the 2 variable phases and in the center of the range this difference really piles up. The basic error behind it is likely still present, but it does not come up over such a short range, but now comes one by one as tiny (e.g. 0.01 ppm range) steps. So it's more like a gain contribution and a little DNL instead of a INL problem from hundreds of such steps at once. -
Thank you for the extra info. I was wondering what the bootstrapped amplifier was for, and 'getting the best possible input common mode to reduce distortion' makes a lot of sense.
I noticed that some photos in the Projects thread appeared to show a CPLD, but you're now using an AVR and Assembly code to do the timing. I totally accept that careful assembly code will provide accurate timing, but I wonder whether the reduced latencies of a CPLD offer any benefit?
Also, it looks like you're using the internal bandgap reference inside the AVR for the auxiliary ADC (and maybe comparator?). These can be quite poor performers, so have you considered the pleasantly ridiculous notion of deriving a reference from the LM399
? Or is the drift small enough that it doesn't matter?
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I am currently using the 5 V regulator as reference for the µC internal ADC. However this µC internal ADC is only good for the lower 7-8 bits (noise wise only 4). So the drift is not that important and for the longer term there is an extra measurement for the scale factor anyway. On the board I have resistors to set the µC reference from the LM399, but not yet populated.
The comparator is using the 5 V for level shifting only, so ideally the effect on both sides would cancel. In addition the comparator is only for the first approximation. A small error from the comparator will be corrected by the ADC reading. The actually used part from the µC internal ADC is only some 7-8 bits, so there is some head room for corrections and comparator drift and noise. The µC internal comparator works surprisingly good, so the first 21 bits set by the classical part with run-up and rundown show very little noise at the edge.
A CPLD could offer a faster reaction to the comparator and thus less latency. This would help a little by reducing the time for the small slope rundown part from currently some 20 µs to some 10 µs, or possibly avoid the slow phase all together. However the gain cal may still need a fine reference level, this could be through the normal input path. It could also provide a little more resolution from the rundown. However the ADC part can make up for this. The noise limit is at some 24-25 bits, so it does not matter if the nominal resolution (before noise) is at 28 , 29 or 30 bits. On the downside a CPLD would need an external comparator and ADC. The µC is not that bad with latency (some 6 cycles). The µC does not even need a very high clock - the external clock unit I currently use just happened to be 16 MHz. It also worked Ok with a 8 MHz crystal (going to the faster canned oscillator did not really help much - just a little fast rundown). The comparator itself can have some extra delay.
For very fast conversions the part of controlling the UART in the background can be a little tricky, so the modulation speed is limited with the µC. Though using quite fast (10 MHZ GBW) OPs the analog integrator seem to be still the limit and I don't see a need for super fast modulation with my ADC. I currently use some 40 kHz and could go to about 200 kHz - with a faster integrator possibly some 500 kHz. However faster modulation can also cause extra noise and INL. For precision I more prefer a slower modulation. -
Despite the simple hardware (about as simple as a good multi-slope ADC can be) the noise of the ADC itself is quite low. Currently I get a little below 1 µV RMS for 1 PLC auto zero readings, good enough for 7 digit resolution and often more limited by the reference.
Could you please explain a bit more in detail how the noise of ADC was measured? -
Noise is measured with a shorted input (select the zero input or input at GND). The noise is than calculated from the standard deviation value over some 100-1000 samples. It can be done for a few different cases, that give slightly different numbers:
1) just simple readings (non AZ). This adds 1/f noise, so noise gets higher with longer time window. One may have to subtract the drift for longer windows.
2) use the difference of 2 consecutive readings (simple auto zero case). This corresponds to the Allan deviation for 20 ms. Ideally 1.4 times the RMS value of single readings, if there is no 1/f noise.
3) use 3 readings as U2 - 0.5*(u1+u3) , as a kind of auto zero with a little filtering for the zero (u1 and u3). This should be about 15% less noise than the simple AZ case.
When reading the ADC's own 7 V reference the noise is slightly (some 20%) higher - not sure why. When reading an external voltage the reference noise adds quite a bit of noise.
For a quick estimate 1/6 the peak to peak value can be used for the RMS noise. So one can get an estimate from the curve before that shows the difference to an exponential decay.
So far the readings are usually with 20 ms (1 PLC) integration. If there is not much correlated noise after AZ, the simple AZ reading are independent and thus the noise is expected to go down with the square root on the integration time. So about 1/3 the noise for the average of 10 and 1/10 the noise for the average of 100 conversions. Due to temperature fluctuations and similar there can be slightly higher noise (added 1/f type noise) over longer times. -
I definitely have to look at better resistors. Currently I have cheap 15 ppm/K class thin film resistor for the 7(6) critical ones. I had hoped for better performance, as the 100 ppm/K grade ones I had used before where about as good. I probably just got lucky there. Besides the gain drift with external temperature, there is another related problem: the input current heats up the resistor R1 and this changes gain.This gives a u³ contribution to INL. So the resistor R1 can be quite important, it just has to be linear.
For the resistors at the input, there are resistor arrays (e.g. 4 x 50 K or 8 x 20 K / 50 K) as a good option. However the reference amplification gets a little tricky, as here I need something like 5 K - 5 K and 9.5-9.7 K (or 10.5 K). This is not a standard array, and combining the array and an extra resistor is also not that good.
There is a work around for the resistor effect. One can measure the ADC gain in real time. So the sequence is not just 0 V and signal, but 0 V - signal and 7 V (raw ref.). This is not a new idea: old DMMs like the Keithley 19x series (and likely the 2001 too) have used this. The down-side is it slows down the measurement and adds some noise. As my ADC is low noise to start with and with only a LM399 reference, this option is not that bad, especially for slower measurements (e.g. > 10 PLC). It essentially doubles the ADC noise contribution for a measurement at 10 V, but here the LM399 is usually more noisy than the ADC anyway, especially at longer integration when 1/f noise from the reference plays a big role.
Besides the external temperature effect this could also correct for some of the self heating of the input resistor.
The µC part already includes such a mode with a 3 conversion sequence. This mode was already used for the plot in the 1st post. Attached is a curve showing the heating effect. The sequence is signal - 0 - ref, with the signal either at 0 or 7 V. Plotted is the relative change in the difference ref-0. Even with a slightly better resistor, there is quite some effect (some 5-6 ppm).
It turned out that the bootstrapped supply for the buffer amplifier is not as simple as it looks. As shown in the plan, it's just at the edge to oscillation (a few more pF of parasitic capacitance can make a different). For stability something like 150 Ohms+1 nF from the OPs supply to ground helps. However this reduces the slew rate the supply can follow and can cause little spikes of current at the input on larger jumps (e.g. 0 V to 7 V).
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The way the +ve and -be resistors are held at constant V / constant I is a really nice feature of this ADC architecture. If cost were no object, one could buy excellent Vishay resistors...
Is it effective to simply use a larger package to reduce self heating?
Alternatively, is there any mileage in thermally compensating the R1 temperature rise? Maybe fitting a dummy resistor either side (Rx and Ry) which is driven so that P(R1) + P(Rx) + P(Ry) is constant? Or is that crazy talk? -
Q1: Do you mean R3 or R1 heats up? R1 is wired to Vref+, R3 comes from input buffer (referring your schematics above).
Q2: why the R1/R2/R3 are of the same value?
Q3: do you use 1n4148 in the power source (graetz)? Those diodes are pretty fast and without parallel caps (ie. a few nF) they may create emi mess in delicate circuits.
Bootstrapped opamp oscillation - in my "simple AFE" simulations I saw the oscillation too. Not always, but at specific input voltages. My AFE has got an opamp to deload the input buffer (low value divider follows). What helped in simulation was to wire a few nF from the Q1/3 base to respective power rail. It could be it is the same in the end effect as you have proposed. -
The self heating problem is with R3 of cause / mixed up the number, sorry for confusion.
It can help to have a larger form factor to reduce self heating. My current board has enough space to use precision wire wound resistors (e.g. Ultra Ohms). One could also use 4 resistors as 2 parallel and 2 in series for R3. R1 and R2 see an essentially constant current and this way should have no heating problem. The constant current also helps with the reference amplifier / inverter, so the slow OP07 should be good enough.
I also though about power compensation as a last resort, especially with resistor arrays like NOMAC. One could use 2 resistors (e.g. 20 K) in series each for R1-R3 and have the last 2 resistors in parallel for power compensation from a 5 V DAC. The ADC could calculate (use a table) the suitable power based on the measured voltage. Also using the AZ phase gives enough power from a 5 V source.
The input part uses fast diodes, to keep the option to use a high frequency transformer instead of 50 Hz. I don't think fast diodes are a special problem - it is more that slow diodes can under certain conditions cause trouble with reverse recovery spikes in some cases. Currently with a 18 V transformer I have extra series resistors at the transformer to reduce the voltage a little, so no sharp current spikes.
R1,R2,R3 are of the same value, so that the switch resistance (some 70 Ohms with HC4053) has the same proportion to the total resistance. This helps to keep TC matching, otherwise the high TC of the on resistance of some 6000 ppm/K could become an issue. With same resistors the switch parts cancel out to a large part.
In my simulations the buffer problem did not show up, it only happened with the real thing. Loading the output too much is definitely a factor. For just -11 V one could still use the OPA145 or OPA1641 directly from the +-15 V - they are not that bad with linearity, tough both at different points (the OPA145/OPA140 have higher gain and the OPA1641 has better CMRR). -
The PC side program is currently written in Turbo Pascal. The software assumes a build in RS232. So for modern PCs it would need to be rewritten, e.g. to support an USB to UART bridge.
You can read from serial port by opening a pseudo-file named "COM1"/"COM2"/... and reading like any other file. That ought to give you access to all serial ports supported by Windows, including USB.
Baud rate would need to be set manually with the MODE command or Device Manager. -
I remembered an interesting part which could be useful for the input resistor: a SMT chip ceramic thermal jumper. Maybe sucking some of the heat away from the resistor into the ground plane would help. Or use them to thermally bond the three integrator input resistors together?
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I remembered an interesting part which could be useful for the input resistor: a SMT chip ceramic thermal jumper. Maybe sucking some of the heat away from the resistor into the ground plane would help. Or use them to thermally bond the three integrator input resistors together?
I tried to google thermal jumper, doesnt look like its in production
. not on digikey too
otoh, I remember a vishay article about smd resistors. a 1206 has about 157C/W. so there is no way around this (even with thermal jumper) unless the part is parralleled on a larger copper plane. -
For the self heating problem I see several solutions:
- using precision wire wound resistors with a lower TC and there relative large form factor. I have space for these on the board.
- use a resistor network with good thermal coupling and TC matching. Due to thermal coupling it's TC matching that matters
I currently have a footprint for a NOMCA resistor network on board - just forgot to order them
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However this still leaves the reference scaling.
- with a resistor array there is the option to use power compensation via software: a 4 th resistor is used to keep the total power per array constant. The µC can calculate the needed power and output that via a 8 bit DAC.
- measure the ADC gain for every conversion, like the old Keithly 19x did. This is especially a low cost option. Due to the very low noise of the ADC the extra noise is not that much compared to a LM399.
This compensates both the self heating and changes due to external temperature changes, not just for the integrator input, but also the reference scaling. This option can still be used with better resistors.
For the time being I go for the last version. So just the extra measurement and math.
With separate resistors the thermal coupling tends to be too slow to be really helpful. The thermal time constant is just a little too large to ensure the temperature is the same, not only over a long time. The resistor arrays tend to be small enough to get thermal time constants of less than 1 second for the internal coupling. So the small size of the resistor element also has advantages. It is still not perfect, but should be good enough for the slower measurements where ppm matter. The fast response can be a slight problem for the correction method however, that has a delay of some 40 ms.
There may be an option to use a symmetric reference (so no more odd +14 and -13.3 V) with not much extra noise. With good timing and adjustment of the pot the smaller slope is not really needed.
This makes it possibly to build a next version with just 2 (or maybe 3, as LT5400 is not available in 50 K) resistor arrays of 4 equal resistors each for all the critical resistors.
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I tried to google thermal jumper, doesnt look like its in production
They are "on order":. not on digikey too
https://eu.mouser.com/Thermal-Management/Thermal-Cutoffs/_/N-5gfz?Keyword=tjc&FS=True
These should be very useful for other things such as thermally equalizing input pads or switch pads. -
It had been discussed in the Multislope topic some time back, but let me kindly ask whether the runup is still as follows:
You do 20ms long measurement, 800 phases, 25us each (==40kHz modulation)
Pseudocode:
pos_phase = 0; // positive REF counter
// do 800 loops, 25us each == 20ms
for (phase_num=0; phase_num<800; phase_num++) {
1. set REFP for 2.5us long;
2. based on comparator output set REFP or REFN, if REFP then ++pos_phase;
3. wait 10us;
4. set REFN for 2.5us long;
5. based on comparator output set REFN or REFP, if REFP then ++pos_phase;
6. wait 10us;
}
result_POS = pos_phase;
result_NEG = 800 - pos_phase;
The Comparator output synced with rising clock edge (ie clock = 2.5us period)
Is that somehow correct? -
It had been discussed in the Multislope topic some time back, but let me kindly ask whether the runup is still as follows:
You do 20ms long measurement, 800 phases, 25us each (==40kHz modulation)
Pseudocode:
pos_phase = 0; // positive REF counter
// do 800 loops, 25us each == 20ms
for (phase_num=0; phase_num<800; phase_num++) {
1. set REFP for 2.5us long;
2. based on comparator output set REFP or REFN, if REFP then ++pos_phase;
3. wait 10us;
4. set REFN for 2.5us long;
5. based on comparator output set REFN or REFP, if REFP then ++pos_phase;
6. wait 10us;
}
result_POS = pos_phase;
result_NEG = 800 - pos_phase;
The Comparator output synced with rising clock edge (ie clock = 2.5us period)
Is that somehow correct?
The run-up phase was like this before. The loop with 2 variable phases looks attractive and there even is US patent US5200752 on this. However it caused INL problems, that took me quite some time to find out. For some reason the two variable phases have not exactly the same effect (though the difference is likely more in the short positive and negative rest). The difference is only minute, so it would not matter for a single period, but it does matter in the center of the range when there is a change over from + - to - + for several hundred patterns over a very small voltage range.
The runup is now a little simpler, with only 1 variable phase and shorter fixed phases:
1 µs fixed negative reference
25.125 µs positive or negative depending on a comparator reading
1 µs fixed positive reference
So it's only 795 loops and close to 40 kHz. I may have to adjust it a little to get closer to 20 ms integration time to improve on hum suppression. I have not looked at the exact numbers after making it slower and the 25.125 µs are a poor choice, as it would take nearly 796 loops to get 20 ms.
There is still unused code for a version with 4 comparator tests - it likely would not work well for the same reason as the failure of the 2 test version.
I just saw the comments and constant names are a real mess (I used a rename on the constants and that did part of the mess renaming a part that should not be changed
) . Some confusion in the comment comes from changing from a stronger negative to a stronger negative reference, when going from the bread board to the PCB version.
So I have to give an updated (mainly improved names and comments) version of the ASM program. -
..
The runup is now a little simpler, with only 1 variable phase and shorter fixed phases:
1 µs fixed negative reference
25.125 µs positive or negative depending on a comparator reading
1 µs fixed positive reference
..
Ah, ok. So, today, the best result would be with following runup:
You do 20ms long measurement, 800 phases, 25us each (==40kHz modulation)
Pseudocode:
pos_phase = 0; // positive REF counter
// do 800 loops, 25us each == 20ms
for (phase_num=0; phase_num<800; phase_num++) {
1. set REFN for 1us long;
2. based on comparator output set REFP or REFN, if REFP then pos_phase++;
3. wait 23us;
4. set REFP for 1us long;
}
result_POS = pos_phase;
result_NEG = 800 - pos_phase;
Ok?
BTW, the simulation shows a 60mVpp ripple after REFP/N switching at the integrator's input, which settles in ~700ns, so 1uS is the max I would go. Have you seen something similar in your hw?
The rundown: now, except various ADC measurements you do at various stages, could you describe - in a similar way as we did above - the rundown phase, for example from the point you have passed the above runup and..
1. you switch the input off
2. you .. -
At the integrator input I get a switching peak of some 50 mV that decays in some 500 ns, so maybe a little faster than the simulation. The 1 µs min pluse ,length may in deed be at the lower end, but so far is see not much INL problems even with only 750 ns. For a linearity check I compare the result of 2 rundup versions, the second one is faster with 1/3 the total loop length and some 750 ns for the fixed parts. Ideally the difference is only due to charge injection and constant. This test revealed the problem with the 4 step pattern, just it did not directly show what the reason was.
The run down is relatively simple. A µC timer is used as a clock, so that I don't need to count during waiting times. The sequence is as follows in a pseudo code:
set switches to input off and positive reference
start timer from 0
wait a little to get min lenght (min 1 µs)
wait for comparator positive (integrator output negative)
set switches to input off and negative reference
T1 := read timer1
wait for comparator negative
set switches to input off and positive + negative reference
T2 := read timer1
wait for comparator negative
set switches to input off and no reference (hold state)
T3 := read timer1
Wait for fixed timer value (via OC1A value)
start µC internal ADC
wait for sampling time of ADC (1.5 +1 ADC clock cycles)
Send run-up data to UART buffer
T_pos := T1 + T3-T2 to UART buffer
T_neg := T3-T1 to UART buffer
read old ADC value (before conversion) to UART buffer
In the current form I do 2 more conversions of the µC internal ADC: First the conversion started at end of rundown is waited for. This way the data are already there and the data format can be simpler. Than another conversion for an auxiliary channel is done, to read the average integrator voltage - this gives a hint on possible DA related error. This part is no longer needed (but still left there), as the test showed essentially no DA related error.
Than the ADC is started again for the conversion before the next run-up.
A weak point of the AVR is that the ADC clock runs through and there is no easy sync with this clock. So the constant waiting time does not make that much sense, unless one would make sure the timing a multiple of 64 cycles. It may be an option to simple start the ADC from scratch (with some extra delay for init). The waiting time is needed for the relatively slow amplifier at the ADC to settle and also the fast part of the DA has time to settle. This could be a small advantage over the classical multi-slope ADC.
-
This is a typical ripple I see on the integrator's input.
It is with ferrite beads and C17 ser R20.
I updated the .asc in Multislope thread.
Syncing an MCU's ADC with such external events is difficult. Therefore I used to use an external 12bit SPI ADC (MAX...) with its own Vreference, while the ADC was driven directly from FPGA. The actual ADC verilog code and FPGA resources are pretty small.