Multislope Design

[Kleinstein]

The ADA4625 is a really low noise OP - but also take quite some current.  To make full use of it one should also change the NE5534, as for the high frequency part these two work together. The LT1037 was a poor choice, because it's not unitiy gain stable. An OPA209 might work (if the input impedance is low enough) - it may need an extra cap to reduce the speed. Changing only the post amplification does not help, as the AD744 is much higher noise.  In the ADC circuit, it depends also on other factors if lower high frequency noise really results in much lower overall noise.

[saturnin]

Yes, ADA4625 is rather hungry if we are talking about supply current (Iq~4.0 mA), but AD744 takes 3.5 mA already. Still better than ADA4627 (Iq~7.0 mA!)

I know LT1037 is stable with gains of 5 or greater. In the slope amplifier, its gain is set to 6 in vicinity of zero-crossing (gain resistors 49k9 and 10k). I ran a simple simulation, didn't see any issue at first glance, so I tried it. As I said, the result was not a disaster, just slightly worse (~20%) than with NE5534.
Maybe LT1037 was too fast? NE5534 uses 47p compensation capacitor, which should give ~4V/us slew rate. I admit I don't get why high slew rate is an issue in this case...I should study some theory 

I would remark I am quite happy with modifications I have already made. I managed to reduce noise from 0.55 uV rms to 0.31 uV rms (@ 10V range, 0V input, 10NPLC, 1024 samples).

[Kleinstein]

Getting 310 nV_RMS at 10 PLC is already quite good, something around 100 nV/Sqrt(Hz) for 1 single conversion or 140 nV/sqrt(Hz) with AZ mode.

The expected noise from the ADA4077 would be about  0.3 pA/sqrt(Hz) times about 50 kOhm (depends on the ADC circuit) and twice the OPs noise at about 2-5 Hz, thus  2 times maybe 15 nV/sqrt(Hz).  This would be total of maybe 35 nV/sqrt(Hz) and thus only a small fraction of the residual noise.

There are also other noise sources. One that is hard to avoid is the input resistors.  Effectively one has the input and a reference path resistor in series. Thus possibly some 40-60nV/sqrt(Hz) from the resistors alone, thus about 1/4 the observed noise.

The effect of the higher frequency noise of the integrator and slope amplifier and thus likely the AD744 would depend on the integration time: it limits the accuracy the residual charge can be determined. It somewhat depends on the exact mode, but the more usual way would be that this noise contribution goes down with one over integration time. So it would be most important at high sampling rates. Chances are it would not matter very much at 10 PLC - especially if the 10 PLC are real single conversions and not averaging over shorter conversions. So comparing the noise at different PLC settings could give some clues on the noise sources.

For using the LT1037 it could  be ringing that can be higher than with a well compensated NE5534. The noise of this OP is still small compared to the noise of the AD744. It is well possible the NE5534 will set the bandwidth for the comparator path - a faster OP would result in a higher BW and thus more noise seen by the comparator. The compensation not only sets the slew rate but also the bandwidth for the OP. If the ADC uses a slow rundown slope, I would not expect the slew rate to be relevant. I don't have an accurate way to calculate the noise from the higher frequency part of the integrator, but I would expect something like  OP_s higher frequency noise for the integrator and post amplifier combined times the square root of the bandwidth (e.g. post amplification) and the time constant of the integrator (cap time resistor at the input path) to be  the main factors. Replacing the AD744 with something lower noise might bring down that noise component by a factor of maybe 3. Reducing the BW is tricky as this might require longer delays and thus a slower rundown phase.

When building your own ADC, reducing the BW might be one option.

[Kleinstein]

I looked at the specs of the Keithley 2010. They show the noise at 0.1 PLC nearly 8 times higher than with 1 PLC. This kind of suggests the noise from the rundown phase is a major contribution at 0.1 PLC, and already present with 1 PLC.  However there is still a chance this is more like quantization noise and not the AD744.

The specs also suggest that the longest integration time directly supported might be 5 PLC and thus 10 PLC would be 2 readings at 5 PLC averaged. This makes sense since at some point the 1/f noise contribution (e.g. current noise from the OP177) would dominate over the noise from the rundown phase.

[saturnin]

The most likely KEI2010 supports true (not averaged) 10 NPLC. It can be set only via GPIB/RS232 though. Supported range of values is 0.01-10.00. You can set e.g. 9.63 NPLC. I wonder why they chose slow rate to be 5 NPLC. I would prefer 10 NPLC as it is in KEI2000/2015 (they use the same ASIC to control A/D conversion).

I found an OPA140, which left after an old project. Couldn't resist and replaced AD744 with it  The result? The noise was further reduced to 0.28 uV rms (it is the average from ten runs, 1024 samples taken in each run, conditions same as above). Next step is clear, I will try to upgrade the slope amplifier too. OPA209 suggested by Kleinstein (thanks!) looks really good...

[Kleinstein]

Upgrading the slope amplifier would not give such a big advantage. A first and easier step could be changing the 47 K / 10 k resistors at the slope amplifier to maybe half (e.g. add another pair in parallel).  A little extra capacitance in parallel to the higher resistor might help to bring back the BW to the correct value.

The 10 K resistor produces more noise than the NE5534 and OPA140 together. The OPA209 would only be better with reduced resistance, otherwise current noise would cause more noise. Anyway the NE5534 is already lower in noise than the OPA140 - so no real need to change the NE5534.

I won't expect a large effect of the fast OP on the noise at 10 PLC. The effect should be more pronounced for the shorter integration times. So it would be interesting to look at something like 1PLC and 0.1 PLC noise, before changing the resistors.

p.s.:
A remark on the integration times. There are two noise sources that change with the integration time: one is the 1/f noise of the "slow" OP (the OP177 in the original circuit)  this noise gets higher for long integration in one piece. The second is the residual charge measurement (e.g. due to the integrator, slope amp, ..) - this gets higher at short integration. With long integration times one usually used the AZ mode, thus alternating between the signal and a zero. There is a point at which it is lower noise to use several conversions and average instead of a single long conversion. There is a good chance this point of the optimum integration time could be in the range of 1-5 PLC - this is especially true for modern DMMs with a focus on fast conversions.

[Kleinstein]

One more thought on the resistor noise: making the 10K/47 K feedback circuit much lower impedance is limited, as more current will flow and this could lead to more "noise"/crap on the supply. One possible solution to avoid a much higher current and much of the resistor noise could be using 2 depletion mode FETs (e.g. JFETs) with a resistor in between in a kind of current limiting circuit - near zero crossing this can be low resistance (e.g. 1 K range). It is nonlinear, but this is not a problem, more like adding to the nonlinear function of the limiting diodes.

Attached is the suggested circuit for the inverting slope amp case, the non inverting is analog.  The choice of JFETs also sets the resistor. A type with low threshold is likely preferred.

p.s.: The red curve shown the input current. Full scale is +-2.4 mA.

[saturnin]

Happy New Year to everyone! 

Interesting idea about feedback resistors and JFETs. I would rather not to change topology of the ADC circuitry in KEI2010 (prefer 1:1 replacement). Definitely inspiring for new designs though.

I performed more tests with various NPLC settings with my modified KEI2010:

NPLC    test result     specs
0.01        63 uV         135 uV
0.1          11 uV           11 uV
1          0.66 uV          1.4 uV
5          0.38 uV          1.2 uV
10        0.28 uV           N/A

I am surprised there is no improvement at 0.1 NPLC at all. Otherwise I am pretty satisfied with results. It is worth to note I have made more modifications than I mentioned here. (I don't want to spam in this thread. I will rather enter a new post once I am finished with performance tests.)

I also tried to find out what slope amplifier is used in DMM7510. I would bet it is AD847J - as it can be seen (with some imagination ) in attached picture stolen from Dave's teardown video. So, they used 2xOPA140 as a composite integrator, AD847J as a slope amplifier (with 49K9, 10K gain resistors) and LT1116 as a comparator. The last two are used in KEI2002 too, so not such surprise.

[Kleinstein]

It is really odd to see not improvement in the 0.1 PLC case. Maybe one could look at a time series or histogram plot, to see if there is something special happening, like a special point of hitting a kind of idle tone and this way a point with poor DNL.

After changing something at the ADC it would be a good idea to at least do some DNL tests with histograms. The histogram might also show if there is even a chance to get better or if quantization limit might already be reached.

The improvement at 0.01 PLC with about a factor of 2 over the specs looks quite good. This is actually a little more than I would expect from changing from an 16 nV/Sqrt(Hz) OP to a 6 nV/Sqrt(Hz) OP with still the 10 K resistor (and thus 13 nV/sqrt(Hz) of noise). There is some extra noise gain due the input capacitance to ground, that might explain why the integrator OP is slightly more important than the slope amplifier and resistor. This noise gain might also explain why they can get away with an OP that is not unity gain stable.  Also the specs are likely a bit conservative.

One might still change the 10K/47 K resistor pair to some lower value, but keep in mind it might also have negative effects due to more stress on the decoupling. The JFETs part was an idea to get a low impedance for low noise and still not so much more current it's not really changing the topology - it's just a nonlinear "resistor" replacement (or in parallel) for the 10 K. I can fully understand if you keep it this way.

Usually the better way to test such things would be a really self made ADC. I thought about an ADC design even before this thread. This kind of explains why I had some points at hand so fast. My concept is a little in between the 34401 and K2000 ADC, with an µC (AVR) for control. This could be good at intermediate integration times (e.g. 1 PLC), but with some limitations at the very short integration times. Limitations at long times are not an issue, as averaging is a real alternative - so I see no real need for a true 10 or 100 PLC mode, if resolution at 1 PLC is already high enough.

[David Hess]

One might still change the 10K/47 K resistor pair to some lower value, but keep in mind it might also have negative effects due to more stress on the decoupling.

Excessive load on the output of an integrated operational amplifier will cause offset shifts and other problems due to self heating from the output transistors.  This is what ultimately limits open loop gain and settling time and why higher noise OP-07 type amplifiers and lower power parts can achieve better precision than OP-27 type amplifiers and higher power parts which require a much lower impedance feedback network to take advantage of their lower noise.  Using an external buffer to unload the amplifier output from its own feedback network and other loads largely if not completely solves this.

Precision operational amplifiers use a mirrored layout of the input differential pair (actually four transistors), the output transistors, and other functions to reduce thermal feedback but this only goes so far.  George Erdi came up with this designing the uA725 at Fairchild in 1969 and then moved to PMI where he used the same design ideas for the OP-07 and its predecessors.

[Kleinstein]

The Keithley 2010 uses a non inverting slope amplifier. So the extra current would come from the slope amplifier (NE5534), that is running rather hot anyway. The problem is more that the current would also flow through ground and this way could cause some trouble.

Somewhat sorry for confusing with showing the inverting version for a slope amplifier - in this case the current would actually come from the integrator, and loading the integrator could be a problem. I would not worry so much about thermal effects (as there is a second OP that takes care of the DC part anyway). However loading could change the open loop gain and add to AC supply currents.

Anyway for experiments around an multi slope ADC a own design would be much more suitable than a precious DMM. Especially with the Keithley meter there is also the somewhat odd way they do the AZ calculation that add low frequency noise - this can also make the interpretation of the readings more difficult.

[new299]

Hi All,

Happy new year, and thank you for your many notes. I'm slowly understanding things better. In the attached schematic I've added a second opamp to the integrator which could be used to compensate for low frequency noise as suggested. All opamps are labelled as AD711s, but I would plan to try the various combinations suggested.

I've replaced the analog switches (DG4xxs) with JFETs. The Keithley 2001 appears to use JFETs driven by a LM339, and I've used the same scheme here. An example of the driver circuit is shown in the bottom left. Will this scheme work here? Which JFETs might be appropriate here?

Thanks again for all your help.

[Kleinstein]

I personly don't like switching with JFETs very much. It's quite an effort needed to drive the gates.  Fast switching and protection against excess gate current are kind of difficult to bring together.  Switching at the negative side would also need a voltage lower than the negative ref. voltage, witch kind of limits the useful voltage range. The choice of p-channel JFETs is very limited. JFETs also tend to have quite a spread in properties.
I would not consider the ADC in the K2001 a good solution - OK to learn from, but not to copy. They still use MOSFETs for the fast switching for the main feedback.

Switching at the very input is odd - the FET towards ground should be behind the other one - otherwise it would shorten the input and leave to OPs input open. There usually is no need for the same magnitude slow slope both positive and negative.

The switch for the zero phase might show too much leakage - so it usually take 2 or even 3 switches combined and a series resistor. If the zero comes from behind the post amplifier, it will also correct for offset drift of that OP. 

It is also odd to have switching for the reference current at both ends - the more usual way is using switches only at one side of the resistor. So either one reference resistor and switching at the +- Ref side or using 2 separate resistors for + and - Ref and use switches at the integrator. Switching at the integrator is kind of a little easier, as the level is near ground.  It is also a good idea to have some balance in the switch resistance, which is easier, when switching is at the integrator side. However switching at the +- Ref side can be lower resistance, but this is usually with MOSFETs instead of JFETs.

[new299]

Thanks for your comments Kleinstein. In the attached schematic, I've reverted back to the DG419.

Based on your preiovus notes, I feel I have a better understanding of opamp selection here. But the switching is less clear to me. I would guess the on resistance isn't very critical, as this can be corrected for with the zero compensation. Various keithley instruments use the SD5400, this doesn't appear to be generally available but the datasheet quotes "Low Interelectrode Capacitance and Leakage", and I'm assuming the capacitance of the device is important?

[Kleinstein]

Keithley used the SD5400 for switching. These are 4 MOSFETs with separate substrate connection, which makes them somewhat similar to half a CMOS switch. AFAIK these chips tend to get obsolete. In addition they need the extra gate to control the 2 MOSFETs. Ready made SPDT CMOS switches are relatively similar and easier to use, though in theory the N-Channel FET only version might have a slight advantage of less controlling capacitance. Still I would consider the DG419 a reasonable replacement, as the ready made chips also include the gate drivers and make the circuit more compact. These switches also provide a reasonable break before make timing.

Though I am not so sure the DG419 is the best choice, as this is a rather high voltage version with thus more charge injection and internal capacitive coupling - there might be other alternatives with better parameters (e.g. max4053, ADG633). Even the 74HC4053 seem to work in the 34401. The on resistance can be important, but so does the change injection or more specific the fluctuations of the charge injection. One has to find a kind of balance between on resistance and charge injection. The on resistance is in series with the current setting resistors and can add quite a bit to the temperature coefficient. However most of that resistance can be balanced to compensate (in the 34401 they have a non operated switch in series just for compensation). This makes it attractive to have the 3 important switches in one chip and also use the same resistance for the reference and signal channels (R2=R3=R4). As the switch is keeping the input side at low voltage, there is no need for the switches to be made for a high operating voltage. Switches for lower voltage (e.g. 5 V or 12 V) often are better with charge injection.

There is no need for both polarities for the fine slope, one is enough. Having less switches at the integrator is attractive, as this reduces leakage and capacitance. I even think one can get away without an dedicated extra switch for the slow slope, if the two reference voltage are slightly different (e.g. +10 V and -11 V). When turning on both at the same time, this corresponds to a -1 V reference and thus a slower slope. For the coarse steps the relevant reference is the difference of the two ref voltages. Due to tolerances one can not rely on the two reference currents to be absolutely equal anyway and thus needs to consider different values anyway - which is easy as it only adds a small offset.

P.S.: one more point: when doing the switching at the integrator side, most of the meters have a ferrite bead or similar between switches and the integrator. This is likely to reduce the effect of charge spikes from charge injection. The exact function is still not clear to me, but it kind of makes sense.

[new299]

Thanks Kleinstein,

I've made a first crack at a layout attached. The second fine slope is present, but I will remove it in a future revision. I've used DG419s and a DG417 for the integrator switch. Analog do a low on resistance version of the DG419 (2Ohms on resistance, ADG1419) in the same package. I'm wondering if this is worth trying out.

As you can probably see, I'm still a bit confused about the grounding. I've tried using star grounding for all the grounds, but I'm less clear on what should happen with opamps. I've therefore pulled all the negative opamp rails back to the same point too. But this is perhaps not necessary?

I still need to think about the integrator capacitor selection, it's laid out for something like a SMD NP0, but I should probably modify the layout so a through hole PP could be used too.

[Kleinstein]

Grounding and similar layout parts are really a difficult part of the design, but it is likely important to get really good performance. I would not be so much concerned about DC shifts, as there will be an offset to zeroed out anyway. Howver anything that changes can be tricky and also those nasty switching spikes can be difficult. So good decoupling is likely needed, especially for the switches, but also for the OPs.

The OPs would rund for most of the part on a +-15 V or similar supply. So the first line of decoupling would be from the +15 to the -15 V at the OPs. For the critical parts (sensitive points, but also noisy ones) one might consider extra isolating impedance (small resistors or ferrites) towards the global power. However there also needs to be a coupling from the supply (usually the negative side) to ground.

I don't think very low resistance switches like the ADG1419 are a good idea. A low resistance comes at the price of more leakage, more charge injection (or at least fluctuations if there is good compensation) and also stronger supply spikes on switching. Quite often the low resistance parts are also slower. Leakage and change injection are a little less critical when switching at the reference side - so at that position lower resistance part might be acceptable.  For switching at the integrator, it is more like looking for lower voltage parts like ADG633. There are also different requirements for the different switches - the fine slope and zero switch don't have to be low resistance at all.

Already the DG419 has quite some capacitance, which could be a problem with several of those switches.

[Kleinstein]

Here is my suggestion for a rather simple multislope converter controlled by an µC (AVR Mega 8 or similar). The circuit is simplified by leaving out a few more obvious parts, like the supply and decoupling. A clean supply and good decoupling is likely very important though. The circuit is to a large part inspired by the HP34401 ADC and the more classical multi-slope ADCs like in the Keitley 2000, with rundown phase with fast and slow slope. In addition the µC internal ADC (e.g. 10 Bit) can be used to measure the residual voltage.

The part on the left is an amplifer for the reference voltages. Noted as +-12 V though the right value would be more like +11 V and -12 V, thus two intentionally slightly different values.

IC1 A and IC1 B are the two OPs for the integrator. The 4 inductors at the switches (74HC4053) are ferrite beads inspired by the 34401 design. Not sure they are actually needed of might want parallel resistors in the KOhms range. This would be a part to check with real hardware. There is no extra slow slope, but combining the two slightly different slopes should work as a slow slope as well. The three resistors (shown as 50 K) at the 4053 should be the main critical resistors in the ADC circuit. Using 3 resistors of same value should give reasonable good compensation for the on resistance in the 4053.

IC4 is working as a slope amplifier in inverting configuration. Using the JFETs Q1/Q2 is optional if rather low resistors are used for super low noise - not sure this is really woth it unless one would go for 8 digits.  A first test could use just a resistor here. The inverting slope amplifier has the advantage that the output voltage range is limited to about +- 0.7 V around the ground / reference level. In addition there is little load to the ground / reference level. Here the reference level is set to about 1 V above ground by a divider. This allows to use the µC internal comparator to detect the crossing of the reference level.

As a kind of second amplification stage there is the OP IC6B as an inverting amplifier with an adjustable reference level. This level should be rather close (or identical) to the 1 V level used for IC4. This amplifier is supposed to be powered from 5 V just like the µC and amplifies the residual charge signal for the µC internal ADC. In addition the inversion is needed to get a hardware zero phase.

Q3 and Q4 (small N-MOS FETs - maybe other types, preferably small ones) are used as a switch for the zero signal. The two fets might be needed for good isolation for good precision. Depending on the mode of operation one might even get away without this HW zero path. R61 is used to add a little bit of negative voltage, to compensate for the shifted reference level used. The zero level would be at about 1/10 (set by R60/R61) of the -12 V reference and thus about 1.2 V (for the ADC) with the resistor values given.

Feedback during the runup phase will be via an extra comparator IC2. Comparison is towards a fraction of the input signal (at LSP1). The combination is also used in the 34401 and many other HP meters, though with using an inverted input signal added to the integrator output. Comparing to the input signal gives kind of a preview to the future integrator state. Due to this kind of preview, the speed of the comparator used for the feedback should not be that important - so chances are one can get away with the lower power 393 instead of the faster, but higher power LM311. Accuracy of FB during runup is not that critical anyway.

AFAIK the AVR µC does not use an internal PLL for it's clock. So I hope to get away without extra synchronization flipflops for the control signal. Depending on the µC used these might be a good idea (for the 2 reference signals). The control is separate to allow for using both refs at the same time.

The one point I am still not sure about is the shifted level for the slope amplifer. One drawback I get, is that the ground of the ADC is somewhat coupled to the µC ground for the µC internal ADC. It also needs quite a lot of extra resistors to shift levels. Maybe there is a better way ? I don't really like the idea of using something like a +-2.5 V supply for the µC, though it might be an option.

From the software side the AVR is fast enough to control the FB during runup. This is with SW in assembler and using the run time for the timing, which is kind of OK as the AVR has a predictable timing (no cache) and the software is not that complicated. Here it is more the integrator HW that sets the speed limit. I would prefer a rate slower than in the 34401, more like the K2000. It looks like the 34401 could use it's high frequency FB only at the price of a reduced input range and long neutral phases - however this adds quite some noise.

For the rundown phase the control by software (instead of dedicated HW) causes some extra delay on the order of 300 ns and thus similar to the delay due to the comparator. I don't think a slightly slower rundown phase should be a problem for a first test. When using the ADC for residual voltage, one might not even need the slow slope (except for super high resolution) and the hardware zero phase.

[new299]

Thanks Kleinstein, the design looks really interesting! It will take me some time to understand it all.

Do you plan to do a layout of this too?

[Kleinstein]

I have a layout ready for a first test board - just need to find time to make the board. It is just for a test and thus has a few air wires to be added.
I also did some minor changes in the circuit.

For the way of operation I am not really sure. I see 2 promising modes of operation. One in the a feedback with reading the comparator at a fixed time to choose between two feedback PWM patterns (like 5% pos and 95% negative, and the other way around). This is about what the 34401 seems to do. This system is the easier one and will be thus my first test.
The other option would be looking also at the time when the comparator changes level and this way get a finer control with many more PWM levels. The second option might give better FB, but it is also computational more demanding and thus can not run that fast.

The HW is rather similar the the 34401: SPDT switches at the integrator. The main differences are:
1) also controlling the signal channel, which is only used for compensation at the 34401. 
   So the ADC will be more classical multislope with a separate rundown phase.
2) using the combination of the both refs to get a fine slope. It is a little higher noise, but not significant, as the fine slope is used only for a short time. It is a rather simple idea so I am surprised I have not found this in the plans of commercial DMMs.
3) using the ADC to measure the voltage after rundown (instead of in the fly in the 34401) - this should give extra resolution and low noise. The µC has the ADC anyway and compared to the comparator the ADC has lower BW, which is good for low noise.

[Kleinstein]

A short update:

I decided to go with a first test on a breadboard (the µC and UART interface is reusing an existing board) version first, with a slightly more simplified version. It uses no external comparator and thus the µC internal comparator for feed-back in the run-up phase too. I know this will lead to some INL/DNL errors due to DA of the integrating cap. However I see not reason an external comparator for a better run-up should not work - this one is not critcal for the final noise.

Anyway the ADC works reasonably, as far as I can tell so far.  Despite of using only a µC clocked at 8 MHz the rundown can be quite fast: about 60 µs - even with some room for improvements.  Currently it seem to be limited by mains hum - so hard to tell how much real noise. So far it's something like 1-5 ppm with a 18 ms integration in a multi-slope mode  and something like a little better than 0.1 % in a dual slope more with 20 µs integration and 60 µs (+ another 40 µs for the µC internal ADC) rundown.

I still need to write some of the GND based part (PC) software and the test measurements to bring the different scales together so it is a little hard to tell how high the noise really is.


Edit:
Attached is a scope picture of the integrator waveform at 20µs/div (500 mV/div ?). The initial sharp rise is the fast "rund-down", followed by an overshoot with fast rundown in the other direction and than a slow rundown (going up) and the horizontal phase (reference off) for the ADC to sample. After that comes the beginning of the next multi-slop run-up that starts as a 100 kHz triangle in this case.  So there is quite some overshoot due to delay of  the comparator (and µC program), but still the rundown can be quite fast. 

[new299]

Hi Kleinstein,

Wow! Sounds like great progress! How do you plan to reduce the mains hum? Would you try integrating over a complete power cycle as a way to attack this?

I would love to see pictures of your build/layout.

Do you plan on eventually making the gerbers available?

[Kleinstein]

The steps to reduce mains hum will be integrating over a full cycle (20 ms) and adding some extra shielding. I had a software bug that made it around 18 ms instead of 20 ms.

Sill better shielding is needed, as to understand the noise it also helps to do measurements with much shorter integration time - up to the point of dual slope mode with very short integration time. With the 1 nF integration cap I could go down to 20 µs integration - though at limited resolution.

Besides better shielding, the next step would be the special modes to measure the reference ratios. Currently I only get raw data, like number of run-up steps, µs of positive and negative reference and the ADC steps.  So it takes three more steps to bring these 4 numbers together.
The step from run-up  steps to µs of pos and neg reference is relatively easy, as this is a fixed integer number that can be determined from the software simulation. The next is getting the ratio of positive to negative reference from a special operation of the ADC - I have the code ready, just have to test it.  For the ADC it might be enough to look at the noise, but for a faster and better value of the scale factor it would also need a special mode of operation.

I will make the layout available - but the current tests might give some changes to the circuit and the board might include something like an input amplifier.
So far the first point to change is that I have hardly a need for the hardware zero mode.

Attached is a picture of the circuit on the breadboard. Form right to left the Chips are:
OP07 to do inversion of the reference voltage (currently 5 V supply or the green LED)
74HC4053 to do the switching
OPA2134 (low noise audio JFET OP, 8 MHz GBW) for both OPs of the integrator
      the integration cap is the small sytroflex one near the scope probe
OP27 used for slope amplification  (slight overkill)
MCP6002 as final amplification for ADC (2. nd OP unused)
The white wire at the left is the output to the µCs ADC. The ribbon cable in the center top is the connection to a µC board with Mega48 µC.

The circuit is running at +-8 V and +5 V, as this are the supply I have at the breadboard.

[Kleinstein]

A short note on progress:
 
The cal measurement to check the ratio of the positive and negative reference seems to work well and fast. So no need for long time stable resistors for the reference amplifier.

The Measurement for the µC internal ADC needs still a few tweaks - it runs through but the numbers still need to make sense.

Noise in the dual slope more is now down very much - good for about 14 bit resolution now.  It looks like some DA effect is visible, but just a little barely at the noise level. It would take a modified SW to get a longer soak time to keep the cap charged for more than about 50 µs.  So the polystyrene cap seems to be good enough.

For the board design I still have a few open points. One is the reference:
I guess I should include a reference on the ADC board. The LM399 is kind of simple, but it is more like long time stable and not really low noise. For the ADC test I would more prefer low noise but no need for long time stability. The long time value and the absolute scale would be due to measuring a reference through the normal input path anyway. My current idea would be something like 3 LM329 refs (essentially similar to LM399 but without the heater and a cheap plastic case and thus not long time stable).  Having 3  refs in series and thus 21 V nominal voltage would reduce the number of critical resistors in the reference amplifiers a little, as there would be little amplification towards the about 25 V difference between the positive and negative reference.

Is there a simple way to to a compensation for the possibly large TC of the LM329 ? I am afraid that buying a few more looking for the 3 refs to compensate is not that practical - chances are a batch from one source would be all one way.

I am currently using normal slow onto-couplers for the UART and thus 9600 baud.  This is just fast enough to send out the data from 20 ms integration in real time. Is there a value in faster transfer, e.g. for 1 ms integration time ? Even when doing the calculation in the µC it would be about 3-4 ms to send out 24 or 32 Bits.

[Kleinstein]

Another update:
I got a first real test in dual slope (no FB during integrate) with putting together the 3 result parts (fast rundown, slow rundown and adc for the residual charge. For a first test I measured the discharge of a capacitor. The plot only shows the last end of the discharge, starting at -300. The y scale is in a kind of arbitray units (around 10 mV at the capacitor), the x scale is just the number of reading (about 15 ms apart). The right graph is a magnified version at the end.

The residual scattering still looks like it contains a kind of dominant frequency, so it is not only noise, but likely still some hum left.