FPGA

Re-enabling JTAG in Altera Max3000A PLDs

SD card/SDIO 3.0 level translation solution

Xilinx ISE 14.7 - IMPACT is a disaster

And the warning is gone ... Simple DivClk by N

Elegant way to select output type from a register or wire ?

Reset in Verilog isn't working as planned

Should I use one big always block or several smaller ones?

Best FPGA for the job - low-speed LVDS deserializer

Planning/design/review for a 6-layer Xilinx Artix-7 board for DIY computer.

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Basys 3 Pmod Tips

A 5V CPLD in 2023?

LPDDR4 memories

Anyone else misses jtag_loader?

timed state machines VHDL

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TVS diodes in FPGA development boards

Disciplined signal clock to PPS

DDR3 Data capture using ISERDESE2

EBAZ4205 questions / problem

Guide: Getting Xilinx ISE to work with Windows 8 / Windows 10 (64-bit)

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Newbie starting using FPGA

Vivado net delay tuning

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OSERDESE2 CLK and CLKDIV phase relation

New FPGAs from Renesas

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ice40 HX, A 5v tolerant FPGA ??

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Troubles while configuring Flex 10K20TC144 in PS mode from microcontroller

JESD204B over fiber

Beginner questions.....

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Efinix

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FPGA recommandations for education

FPGA VGA Controller for 8-bit computer

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Does anyone tried to use OpenAI and ChatGPT to generate Verilog code?

The VHDL poster you didn't know you need

Arrow DECA MAX 10 board for $37

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where to start?

Altera standalone programmer tool, gone from the internet?

TANG Nano 9K - non working external Flash memory (P25Q32SH)

Reading contents of Altera PLD

LCD prj for Altera Cyclon IV do I need to add input/output ports in bsf how

DDR3 Strobe to data timing constrains

Some thoughts on PCI on 3.3V FPGAs